mersault
Member level 2
Hello.
I made a modulator-demodulator binary PAM in a pair of FPGAs. Now, I want to test my design to find the bit error rate (or error probability) versus SNR.
What is a correct procedure to achive a good estimation of the BER?
my method, at this time was the following.
I generated 100 random sequences of ones and zeros, I take an interval of amplitude (1 volt to 0,1 volt with a step of 0,1). Then for one amplitude I take the error average of the 100 sequences. With all the amplitudes I could build a graph.
Is that method correct? There's another "standard" method?
Thank you.
I made a modulator-demodulator binary PAM in a pair of FPGAs. Now, I want to test my design to find the bit error rate (or error probability) versus SNR.
What is a correct procedure to achive a good estimation of the BER?
my method, at this time was the following.
I generated 100 random sequences of ones and zeros, I take an interval of amplitude (1 volt to 0,1 volt with a step of 0,1). Then for one amplitude I take the error average of the 100 sequences. With all the amplitudes I could build a graph.
Is that method correct? There's another "standard" method?
Thank you.