Which data sheet are you looking at?
Looking at
https://ww1.microchip.com/downloads/en/DeviceDoc/39582C.pdf Section 2.2.2.3 on page 24, it shows the INTCON register that contains a number of control bits including PEIE (the peripheral interupt enable) and the TMR0IE which enables the Timer0 interrupt (as well as TMR0IF and other bits). However I would not say that this shows that there is a relation between them.
If you look at Figure 14-10 on page 153, you will see that PEIE does not control the TMR0IE/TMR0IF 'and' gate.
The same figure will show you the answer to the questions in your last paragraph.
Susan