PDK tt_pre vs tt_post

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m3nsh

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In PDKs, the devices models come in different flavors: tt, ss, ff, pre, post.. etc.
My question is what is pre and post? If it's pre-layout and post-layout, what difference is there between the two models?

Thanks!
 

For one thing, parasitic extraction will pick up the poly-
metal, metal-silicon capacitances of the core FET which
are already built into the _pre model. This would be an
added penalty on the post-layout extracted simulation
of RF / fast edge performance.

The _post would remove the amount of double-counted
capacitances to get parity with the _pre result (and
hopefully both have reasonable margin to silicon test).
 
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    m3nsh

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Thank you for your reply.

One more thing: If I'm extracting parasitics by EM simulation of the interconnects, in this case it makes sense to use the _pre all the time, right?
 

_pre would contain the intra-FET metal-poly (as part of cgdo,
cgso) and the EM simulation will also grab that onto the nets
involved. So double counted. I'd use the _post any time you
are doing layout-derived netlists.
 

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