PDK Development for Cadence

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write2rammy

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Hi all,

I have to develop a design kit for printed OFETs. I have a working verilog-A model of these transistors just the static and dynamic model. I have no experience of design kit development. Does anybody know how can I develop a PDK that needs to be integrated within cadence environment? I mean which language to use, what are the essential files that need to be present. Does cadence has any flow for this? Can somone provide me links to any kind of tutorials on this? Thanking you in advance.
 

To be simple, just create a symbol for it with composer, and attach model for it. It can be used for simulation.
However, it is not PDK method.
 

leo_o2 said:
To be simple, just create a symbol for it with composer, and attach model for it. It can be used for simulation.
However, it is not PDK method.
Click to expand...

But how can I map the techonology specific inputs for layout, LVS and DRC?
 

You can also create layout view and copy from foundry's layout. In LVS and DRC command file, new device should be added.
 

Thanbk you Leo. I dont understand your point. Could you elaborate on how to add a new device in LVS and DRC file? Also what do u mean copying from foundry's layout. The fabrication is done internally and all I can have is some microscopy done on the fabricated ckts to get out the process variations.
 

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