You still didn't tell how the observed "timing violations" could happen at all in a 10 MHz SPI interface. For the time being, I assume that the problem is just a misunderstanding of SPI protocol (respectively wrong setup).
If this is a theorectical question about delay equalization, O.K. you can do it. Practically, a signal class like low speed (e.g. < 50 MHz) SPI busses can be routed without length constraints. Crosstalk constraints are probably more important.