PCB related question

[ghasant]

Hello everyone, Being a hardware design engineer, the very first time i am guiding a PCB Design Engineer on a embedded project circuit board. The Processor is interfaced with SPI lines to a Peripheral Device. On the MOSI there is a datasignal of about 10MHZ. But it appears to have the setup violations of about 20ps and hold violation of 400ps.

The question would be, what instruction should be advised to pcb designer to overcome this violations on routing without interfering or software changes Other way is how would be this solved by PCB designer if he is aware of this?

please advise.
Ghasant

 

[FvM]

Probably a misunderstanding of SPI operation. SPI is designed to have setup and hold time of about 1/2 clock cycle by launching data at one clock edge and sampling it at the other edge.

In so far, a 10 MHz SPI interface doesn't require any particular precautions regarding signal timing. If the data transmission fails it's most likely a case of wrong SPI mode setup.

 

[ghasant]

Thank you FVM. But can a PCB designer can solve if there is setup and hold violations by himself. Meaning he should himself overcome the issue.

Please advise.

Regards
Ghasant.

 

[FvM]

High speed designs (DDR, gigabit interfaces) often require delay equalization which is done by routing length constraints. Generating artificial delays is basically possible as well. But 400 ps is a large delay amount (about 65 mm trace length). You really don't want to cobble your board with delay lines to fix chip design faults.

 

[ghasant]

Almost the similar reason was explained by the PCB designer,that Setup and Hold violations are not solvable. But was not agreed... it is still open.

By the way the other question is... In selecting the MOSFET. If i have the Following specs as

Junction Temp=125C
Power consumed=2W
Ambient Temperature=60C

What parameters in the datasheet of MOSFET should be considered such that i should assure the selected MOSFET is excat and it will work.. Generally what are the parameters should i consider in datasheet to select a MOSFET.

Regards
Ghasant.

 

[chuckey]

So for 2W dissipation the junction to free air thermal resistance must be less then 60/2 degrees per watt (TRj-a). Lower would be better. if this can not be realised and a heat sink is required, then two thermal resistance in series must be considered, that of the junction to case (TR j-c), and heatsink to air. The latter can only be found in heat sink manufacturers data sheets.
Frank

 

[ArticCynda]

High speed designs (DDR, gigabit interfaces) often require delay equalization which is done by routing length constraints. Generating artificial delays is basically possible as well. But 400 ps is a large delay amount (about 65 mm trace length). You really don't want to cobble your board with delay lines to fix chip design faults.

Agreed, for a 10 MHz signal I would consider trace equalization a fairly unnecessary complication, at least assuming both ICs are sufficiently close to each other (i.e. centimeters).

A cheat could be to apply a wide differential pair constraint to the SPI lines, to force your router to route them in each others proximity.

 

[ghasant]

Agreed, for a 10 MHz signal I would consider trace equalization a fairly unnecessary complication, at least assuming both ICs are sufficiently close to each other (i.e. centimeters).

A cheat could be to apply a wide differential pair constraint to the SPI lines, to force your router to route them in each others proximity.

Yes, this was the solution given to overcome the violations, but the brainy head shook right and left, instead up and down saying a confident reply ,find out the proper way which has solutions .

 

[FvM]

A cheat could be to apply a wide differential pair constraint to the SPI lines, to force your router to route them in each others proximity.

Surely not a differential pair constraint. It has other purposes than a length constraint. In contrast to a differential pair, you also should worry about unwanted coupling between the SPI lines.

Yes, this was the solution given to overcome the violations, but the brainy head shook right and left, instead up and down saying a confident reply ,find out the proper way which has solutions.

You still didn't tell how the observed "timing violations" could happen at all in a 10 MHz SPI interface. For the time being, I assume that the problem is just a misunderstanding of SPI protocol (respectively wrong setup).

If this is a theorectical question about delay equalization, O.K. you can do it. Practically, a signal class like low speed (e.g. < 50 MHz) SPI busses can be routed without length constraints. Crosstalk constraints are probably more important.

 

[ghasant]

You still didn't tell how the observed "timing violations" could happen at all in a 10 MHz SPI interface. For the time being, I assume that the problem is just a misunderstanding of SPI protocol (respectively wrong setup).

If this is a theorectical question about delay equalization, O.K. you can do it. Practically, a signal class like low speed (e.g. < 50 MHz) SPI busses can be routed without length constraints. Crosstalk constraints are probably more important.

Yes, this was a theoretical question and not sure if this issue was faced. But you had mentioned you can do it. How in theoretical. Could you explain.

Regards
Ghasant

 

[FvM]

I must confess that I have only limited interest to answer theoretical questions, meaningless interview questions etc.

But provided the PCB traces can work as a transmission line in your design (ground plane present, roughly defined impedance, source side impedance matching), you can add respective trace length as delay. Assume 6 ps/mm as a first guess.