Passing RAM as argument in tasks in Verilog

[hassanzia]

HI all.

Is it possible to pass a RAM as an argument in a verilog task. Also can a task return a value as a RAM?

for example is the following code acceptable?

task xyz();

input [7:0] reg_in [0:3];
output [7:0] reg_out [0:3];


endtask

PS can a task return a value (like a C++ function)

 

[FvM]

Similar to modules, Verilog tasks and functions don't provide multi-dimensional vectors as port items. Look for System Verilog features if you want to overcome this restrictions.

There are functions in Verilog, with some restrictions compared to tasks. Consult your Verilog text book or IEEE 1364 for details.