I've recently been trying to write [in Verilog] generic modules that will work as "wrappers" on top of other modules.
e.g. a serial interface module that could contain a basic math module like an adder, multiplier or shift/roll etc.
So, instead of creating a new module for each of them (e.g. serial_adder, serial_multiplier etc),
I was thinking of passing the basic module as a parameter to the generic module (@ instantiation).
I think the following example illustrates the idea (here, the generic module is a register for recursive additions, multiplications etc).