In your figure 1, many people will simulate M1 at the gate level and M2 at the RTL level because they need the performance/capacity. Sometimes there are hundreds of blocks, and simulating them all at the gate-level is too costly, so the pick the blocks then need to perform gate-level simulation and swap them for the RTL. That's what I was referring to.
It wasn't until I saw your figure 2 that I understood what you were asking in your original question. It really doesn't matter to the simulator that you have a gate-level and RTL model, it's just two different models that you want to dynamically switch. Anyone who builds fault tolerant redundant hardware does something like this in their design. It's just that one of your models happens to be gatel-level, the other is RTL.
You've still only explained what you want to do, not why you want to do it. People do not simulate RTL vs gate comparisons anymore, you are only checking the validity of your synthesis tool, and there are formal equivalence tools that can do a much better job than dynamic simulation.