pass a dimentional array(2D) to a function VHDL

[axcelenator]

declared a matrix and a signal in my TOP file like this:

type scanImage is array (0 to 7,0 to 7) of std_logic_vector(2 downto 0);
signal image_matrix : scanImage;
Now, I want to send the above signal to a function which calculates number of cells in the matrix which are not "000".

My package looks like this:

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Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
 use IEEE.std_logic_unsigned.all;
 use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
 USE IEEE.NUMERIC_BIT.ALL;
 
 
PACKAGE my_pack IS
 
type double_array is array (0 to 7,0 to 7) of std_logic_vector(2 downto 0);
 
--------------------square calculation declaration--------------------------
 function square_calculation(matrix : double_array) return integer;
 
 
 ---------------------------------------------------------------------
 function square_calculation(matrix : double_array) return integer IS
 variable tmp: integer range 0 to 64;
 begin
  tmp:=0;
  for i in 0 to 7 loop
 
            for j in 0 to 7 loop
                if matrix(i,j)/="000" then
                    tmp:=tmp+1;
                end if;
            end loop;
 
end loop;
return tmp;
 
end function square_calculation;
 
 END my_pack;

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After compilizing I get this error:

Error (10476): VHDL error at vision_ctrl.vhd(112): type of identifier "image_matrix" does not agree with its usage as "double_array" type

Thanks for helping me.

 

[K-J]

declared a matrix and a signal in my TOP file like this:

type scanImage is array (0 to 7,0 to 7) of std_logic_vector(2 downto 0);
signal image_matrix : scanImage;

<snip>

My package looks like this:
PACKAGE my_pack IS

type double_array is array (0 to 7,0 to 7) of std_logic_vector(2 downto 0);

After compilizing I get this error: Error (10476): VHDL error at vision_ctrl.vhd(112): type of identifier "image_matrix" does not agree with its usage as "double_array" type

The error is because image_matrix is of type 'scanImage' but your function needs type 'double_array'. Just because both types have the same definition, does not mean that they can be assigned to each other. VHDL is a typed language which means that you can't assign one thing to another if they of different types without some conversion function. In this case though, you should probably dump your definition of type 'scanImage' and define image_matrix to be of type 'double_array'

Kevin Jennings

 

[TrickyDicky]

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Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
 use IEEE.std_logic_unsigned.all;
 use IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
 USE IEEE.NUMERIC_BIT.ALL;
[/QUOTE]
 
While on the subject of typing, this massive load of package uses is a fairly standard way to confuse yourself with less than straightforward errors. numeric_std and std_logic_arith both declare types called "signed" and "unsigned". The joy of this is that if you try to use either, you'll get an error about a clash and you wont be able to use either without explicitly declaring which one you meant. 
 
So it is much better just to drop std_logic_arith from your code, as it's not part of the VHDL standard (and neither is std_logic_unsigned for that matter).

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