I use Partial reconfiguration of FPGA to implement two modules.
if the two modules have different number of I/O ports. do i need to match between them?
and it is just a matching to have the same number of ports or also their sequence is must?
It's been years since I used it and I don't recall if there was a way to map the ports if they had different names. If you have an existing module that doesn't have matching port names you can easily write a wrapper to add/remove ports to match and stub off ports properly so the partial design is hooked up correctly.