siddharth3
Newbie level 1
partial place and route
Hello all,
I have been implementing a design on a Xilinx FPGA for a few weeks. Since the rtl is huge it takes arnd 5hrs for synthesis and place and route to complete(1hr+4hr). Everytime there is a small change in the RTL, the whole process needs to be redone and it consumes a lot of time. Is there a way in which i can reduce sysnthesis and place and route time by concentarting on just the block that was changed??? please help me...
Hello all,
I have been implementing a design on a Xilinx FPGA for a few weeks. Since the rtl is huge it takes arnd 5hrs for synthesis and place and route to complete(1hr+4hr). Everytime there is a small change in the RTL, the whole process needs to be redone and it consumes a lot of time. Is there a way in which i can reduce sysnthesis and place and route time by concentarting on just the block that was changed??? please help me...