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partial and dynamic reconfiguration

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deepa

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partial reconfiguration profile

what is the difference between dynamic and partial reconfiguration?
 

delay

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Dynamic means run time, while system is operative.
Partial means part of the resident resources are reprogrammed while other system areas are unaltered.
 

salma ali bakr

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so with SRAM FPGAs, it is all dynamic reconfiguration or did i get that wrong???
 

Ohh

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Here are some simple / basic classification schemes:
* one-time configuration (e..g. using antifuse technologies) != reconfiguration (e.g., using SRAM or Flash memory cells)
* full-chip reconfiguration != partial reconfiguration (some regions of the logic array are selectively reconfigurable)
* static (only one configuration is used) reconfiguration != dynamic or run-time reconfiguration (multiple configurations can be downloaded one after another during the application lifetime)

In general, dynamically reconfigurable (also called run-time reconfigurable) FPGAs are SRAM-based due to their fast configuration memory access (read/write).

Examples of commercially available FPGAs that support both partial and run-time reconfiguration are Xilinx Virtex and Spartan Series (incl. the newer ones) and Atmel AT40K/AT94K (FPSLIC).
 

bjzhangwn

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Ohh said:
Examples of commercially available FPGAs that support both partial and run-time reconfiguration are Xilinx Virtex and Spartan Series (incl. the newer ones) and Atmel AT40K/AT94K (FPSLIC).
Hi,does Lattice and altera fpga have this function?
 

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