Ravinder487
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Now if you talk about Cb value then,I think Cb is hold capacitor here.You need to choose it's value very carefully.Then you are right that node 1 parasitic capacitance effect more because cb remember it's previous effect by internal parasitic capacitance at node 1.And i guess hold capacitor is key concern in gain error.parasitic effect can be minimized by increasing the value of capacitor Cb but can't be eliminated completely.My question is if the value of Cb is fixed due to speed consideration then parasitics at which node(1 or 2) will determine gain error of this S&H