Parametrized busses in Verilog-A

[radius2]

Hi

I'm trying to create an instance with a parametrized bus
in Verilog-A i. e. when I instantiate it in a schematic in cadence,
then there should be a parameter to determine the size of
the bus by clicking on the instance and pressing Q. The idea is to
avoid creating several instances with the same functionality but with different
bus sizes. However, I'm wondering if this is possible. What would
happend with the bus pin when the symbol is created?

I've come across a few ways that give some clues for example:

module adc(out, in, clk);
.
.
parameter integer bits = 8; // resolution (bits)
.
.
output [0:bits-1] out;
electrical [0:bits-1] out;

This however generated the following error:
"Encountered missmatch in size of formal and actual for out,
make sure the size of formal and actual match"

Another example I found, used the line `define bits 8
before the line module adc(out, in, clk);, instead of defining
bits as a parameter. However this doesn't
include the possibility to change the bus size when putting the instance
in the schematic.

So before I discard the idea completely I wanted to ask here if
this is possible to do.

 

[radius2]

I think I found the answer
Verilog-A allows parameterized bus widths for ports and signals.
but the Cadence Verilog-A implementation does not allow this: According
to Cadence Verilog-A reference v11.1 "parameter-sized ports"
are not supported.