I am trying to design a parameterized 1-to-N demultiplexer in Verilog but couldn't come up with proper code for it. I know how to design a dmux but am having trouble with making it parameterized. It would be great if someone could help me out with it.
module dm ( in, sel, out );
parameter N = 4;
localparam SN = clog2(N);
input in;
input [SN-1:0] sel;
output [N-1:0] out;
function integer clog2 (input integer n);
integer j;
begin
n = n - 1;
for (j = 0; n > 0; j = j + 1)
n = n >> 1;
clog2 = j;
end
endfunction
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : dm_out
assign out[i] = sel==i ? in : 1'b0;
end
endgenerate
endmodule
Thanks for the reply,
Is there a way i can assign a value to local parameter as clog2(N) (during compilation) without actually synthesizing it?
bcoz its just a parameter, why synthesize something to assign a value to it?
this function doesn't generate physical logic and is used for local parameter calculation. "synthesizable" in my interpretation - support by synthesis tools.
clogb2 function does not actually synthesize to any actual hardware. Its just a constant function used in order to calculate the complex parameterized values.
During synthesis process, on of the very initial tasks the tool performs is code related processing, i.e. calculation of constants, syntax check, low-effort compile, loop unrolling, subprograms (tasks and functions) expansion, dead code removal, etc. and this is where it actually calculates the value of the parameter through the clogb2 function before performing further RTL level, logic level and gate level synthesis/optimization performing.
In short, you are not inferring any hardware, but just defining the constants in a bit complex way.
---------- Post added at 09:08 ---------- Previous post was at 08:57 ----------
Here's the dmux code that I came up with, it doesnt use clogb2 or generate statements, instead uses a shift operation for constant calculation and a simple always statement
module dmux
#(parameter WIDTH = 4)
(input in,
input [WIDTH-1:0] addr,
output reg [(1<<WIDTH)-1:0] out
);