parallel to parallal state machine to generate parity

[jokester4u]

can someone help me to generate parity with 8 bit of inputs parallel to parallel using state machine using vhdl code?

I have done serial to parallel converter

can someone fix for me ?

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
entity spc_state is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           d_in : in  STD_LOGIC;
           ready : out  STD_LOGIC:='0';
           err : out  STD_LOGIC:='0';
           d_out : out  STD_LOGIC_VECTOR (6 downto 0):="0000000");
end spc_state;
 
architecture Behavioral of spc_state is
 
type state is (idle, one, two, three, four, five, six, seven, eight, nine);
signal pres_state, next_state : state;
signal reg : std_logic_vector (9 downto 1);
 
begin
 
process (clk, rst)
begin
 
if (rst = '1')then
pres_state <= idle;
 
elsif (clk' event and clk = '1') then
pres_state <= next_state;
 
end if;
end process; 
 
process (pres_state, d_in)
begin
 
next_state <= pres_state;
 
case pres_state is 
 
when idle => if d_in = '1' then 
                next_state <= one;
                 else next_state <= idle;
                 end if;
                 
when one => reg(1)<= d_in;
            next_state <= two;
                
when two => reg(2)<= d_in;
            next_state <= three;
                
when three => reg(3)<= d_in;
            next_state <= four;
                
when four => reg(4)<= d_in;
            next_state <= five;
                
when five => reg(5)<= d_in;
            next_state <= six;
                
when six => reg(6)<= d_in;
            next_state <= seven;
                
when seven => reg(7) <= d_in;
            next_state <= eight;
                
when eight => reg(8) <= d_in;
             next_state <= nine;
                 
when nine => reg(9) <= d_in;
             next_state <= idle;
 
when others => next_state <= idle;
 
end case;
end process;
 
process (pres_state)
 
variable temp : std_logic:='0';
variable temp2: std_logic_vector(7 downto 1):="0000000";
begin
 
 
case pres_state is 
 
when idle => temp := reg(1) xor reg(2) xor reg(3) xor reg(4) xor reg(5) xor reg(6) xor reg(7) xor reg(8) xor reg(9);
             err <= temp;
             if temp = '0' then 
                    ready <= '1';
             d_out <= reg(7 downto 1);
                 temp2 := reg(7 downto 1);
                 end if;
 
when others => d_out <= temp2;
 
end case;
 
end process;
 
 
end Behavioral;

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[ads-ee]

You don't say what is wrong, or why you think there is something wrong. Do you have a testbench that shows an error?

I could be wrong but I'd say d_out is going to end up being implemented as a latch as it has to default to holding it's value if temp = '1'.

Most serial to parallel conversions use a shift register+counter instead of a demultiplex+FSM to convert the serial data to parallel.