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Parallel termination on a clock line

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shaiko

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I often see PCB schematics that use single ended clocks with 50 Ohm parallel termination resistors at the Rx end.
The clock buffers are generally 3.3V LVCMOS.
When reading the datasheet of these crystal oscillators I often find the maximum current rating to be around 10mA.

However, if we divide 3.3 by 50 we get 70mA of current conssumption on the termination resistor.

My questions are:

1.Why doesn't the crystal oscillator burn out ?
2.How does the Rx buffer recognize valid logic '1' if the clock's buffer cannot drive enough current to get it to 3.3V ?
 

When people do high speed low-voltage single-ended signaling, they will often have their signals swing about a "reference" voltage, only by a few hundred millivolts. The termination will terminate into a strong reference voltage driver, which can sink or source current, and whose output voltage sits mid-rail.

I am, however, surprised to see that something that can only drive 10mA would be used to drive multiple 50 ohm terminations; are you sure you're looking at the right part number?
 

Termination options have been discussed in a same topic thread. https://www.edaboard.com/threads/256089/

A 3.3 V LVCMOS osciallator won't be terminated with 50 ohm to ground or a reference voltage, because it's beyond specifications At best a dynamic termination with a small series capacitor would be used in some cases.
 
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    ZekeR

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