Parallel stadium of Pipeline

[HyperText]

Hi, I have a Spartan-E3 FPGA and I'm realizing a (parallel) pipeline with 4 stages like this: https://i.imgur.com/6CQNk.png
The two stages "T3" are the same. T1, T2 and T4 "run" at 50MHz, while T3 runs at 25MHz (and 180° shifted like in the figure).

In Behavioral Simulation it works fine, the results are correct. The problem occurs when I try to synthesize this project on my FPGA. In particular I receive these warnings (and offcourse the results produced are wrong):

WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_clk_2/Clock_DCM/CLKFX_BUFG_INST" (output signal=clk_2)
has a mix of clock and non-clock loads. Some of the non-clock loads are
(maximum of 5 listed):
Pin I0 of pipeline/mux3/o<65>1
Pin I0 of pipeline/mux3/o<64>1
Pin I0 of pipeline/mux3/o<17>
Pin I0 of pipeline/mux3/o<18>
Pin I0 of pipeline/mux3/o<20>
WARNING:Route:455 - CLK Net:clk_2 may have excessive skew because
0 CLK pins and 66 NON_CLK pins failed to route using a CLK template.

Where "clk_2" is the CLOCK 25MHz.
This is "my multiplexer": stage_4_in <= stage_3_1_out when clk_2='1' else stage_3_2_out;

Basically I can't drive the Multiplexer Selection with a clock signal. So, how can I do it?
I have to do this: if CLOCK 25MHz is high the mux output has to be the top one; otherwise it has to be the second one (bottom). I couldn't figure out how to do this.

By the way, this is the DCM configuration:

CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => TRUE

Thanks

 

[joelby]

Use clock enables rather than two 25 MHz clocks. At every 50 MHz clock cycle, toggle a register. If it's high, enable one of the Rete3 registers. If it's low, enable the other one.