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The output of the Parallel Port is normally TTL logic levels. The voltage levels are the easy part. The current you can sink and source varies from port to port. Most Parallel Ports implemented in ASIC, can sink and source around 12mA. However these are just some of the figures taken from Data sheets, Sink/Source 6mA, Source 12mA/Sink 20mA, Sink 16mA/Source 4mA, Sink/Source 12mA. As you can see they vary quite a bit. The best bet is to use a buffer, so the least current is drawn from the Parallel Port.
If necasary or you're not worried about damaging your parrallel port too much keep in mind multiple data lines of a parallel port can be tied together to increase the amount of current you can source, though you must be absolutly sure that those lines are always 1 or that they're diode protected to prevent individual data lines from shorting to each other. As said in the previous post, a buffer is always the best idea.
I guess you're asking about the port on the back of a PC.
If your port is IEEE compliant, then the IEEE 1284-2000 standard says this about a Level 1 Device:
8.3.2.1 Driver requirements
a) Drivers shall operate at nominal 5 V TTL levels.
b) The open circuit high-level output voltage shall not exceed 5.5 V.
c) The open circuit low-level output voltage shall be no less than –0.5 V.
d) The high-level output voltage shall be at least 2.4 V at a source current of 0.32 mA.
e) The low-level output voltage shall not exceed 0.4 V at a sink current of 14 mA.
f) Pull-up resistors, if present, shall be not less than 1.8 kΩ ± 5% for control and status signals, and not less than 1.0 kΩ ± 5% for data signals.
g) Circuit and stray capacitance shall not exceed 50 pF of uncompensated capacitance. Additional capacitance may be compensated for by providing additional source and sink currents within the driver circuitry.
And this about Level 2 Device:
8.3.3.1 Driver requirements
a) The open circuit high-level output voltage shall not exceed 5.5 V.
b) The open circuit low-level output voltage shall be no less than –0.5 V.
c) The dc steady-state, high-level output voltage shall be at least 2.4 V at a source current of 14 mA.
d) The dc steady-state, low-level output voltage shall not exceed 0.4 V at a sink current of 14 mA.
e) The driver output impedance (RO in figure 34) shall be 45–55 Ω, at one-half the actual driver VOH minus VOL voltage, (VOH and VOL are the actual measured voltages of the output device). This causes the driver to generate an incident wave slightly in excess of one-half VOH minus VOL amplitude into an infinitely long 62 Ω transmission line, as measured at the driver/cable interface, for transitions in either direction.
f) The driver slew rate shall be 0.05–0.40 V/ns.
The values for items e) and f) are measured at the connector pin under load.
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