Parallel Communication between FPGA

[electrobuz]

I want to send a byte from one fpga and catch it on another. I am using parallel communication for it. In the code below, I want first value being sent to be stored in D1 and the next in D2.

architecture Behavioral of main1 is

signal D1,D2,D3: std_logic_vector(6 downto 0);
signal PState,NState: integer:=0;
signal flag: std_logic:='0';

begin

process(I,PState)
begin

case PState is

when 0 =>
	if I(0) = '1' then
	NState <= 1;
	else
	NState <= 0;
	end if;
	
when 1 =>
	D1(6 downto 0) <= I(7 downto 1);
	flag <= '1';
	NState <= 2; 

when 2 =>
	if flag = '1' then
	D2(6 downto 0) <= I(7 downto 1);
	end if;
	--NState <= 0;
when others=>NULL;

end case;
LED <= D1;
end process;

process(CLK)
begin
      if CLK'event and CLK = '1' then
      PState <= NState;
		end if;
end process;

I am getting the following warning:
"WARNINGhysDesignRules:372 - Gated clock. Clock net NState_or0000 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop."

 

[ads-ee]

You know you have NState in state 2 commented out. So NState will produce a latch, which is probably why you get this cryptic looking warning about NState being a gated clock.. This is one good reason for keeping all the state transition logic in the clocked process.

 

[barry]

Oh, you again.

YOU STILL NEED TO USE A CLOCKED PROCESS!!

 

[electrobuz]

Yeah I had forgotten that I had commented it. The warning is gone now.
But I am doing LED <= D1, still I cannot see anything on the LED's. They are not glowing. What could be the reason?

 

[ads-ee]

Because like everyone keeps telling you in your other thread...

Use a CLOCKED PROCESS.

You've made D1 and D2 combinatorial paths. They can't hold the value you are sending on I. It might help if you actually read the replies in the other thread. Remove the D1, D2, and flag from your combinatorial FSM process.

 

[electrobuz]

Because like everyone keeps telling you in your other thread...

Use a CLOCKED PROCESS.

I did read all the other posts. I am having problem understanding where do use this clocked process? I am making use of one clocked process to change the states. I understand that D1 and D2 are forming a combinatorial path and hence are not storing it. How does using a clocked process rectify this?

 

[barry]

I'm done with him.

 

[ads-ee]

I did read all the other posts. I am having problem understanding where do use this clocked process? I am making use of one clocked process to change the states. I understand that D1 and D2 are forming a combinatorial path and hence are not storing it. How does using a clocked process rectify this?

Do you even understand what a VHDL clocked process is? Maybe you should learn about digital electronics before writing any VHDL code.

Do you understand to store a value for later use you need a register (a memory device)? A clocked process infers registers when synthesized. Do you even understand what synthesis is?

From what I've seen so far:
a) you've been sleeping in your digital engineering classes
b) your a software engineer who can't think hardware
c) not an engineering student but thought it would be great to learn a "programming" language.

If it's a try getting more sleep the night before class.
If it's b VHDL is NOT a software language and doesn't behave like a software language.
If it's c more power to you but like b VHDL isn't a software language.

 

[FvM]

Some things should be fixed in the code, but a gated clock can't be seen.

If the warning really belongs to this piece of code, the gated clock is outside the code snippet, in the place where CLK is generated.

To be fair, at least the state variable is properly registered now, so the code has a chance to run in FPGA hardware (despite of the stuck points). Nevertheless you should get rid of the latches for flag, D1 and D2.

 

[aruipksni]

Some things should be fixed in the code, but a gated clock can't be seen.

If the warning really belongs to this piece of code, the gated clock is outside the code snippet, in the place where CLK is generated.

To be fair, at least the state variable is properly registered now, so the code has a chance to run in FPGA hardware (despite of the stuck points). Nevertheless you should get rid of the latches for flag, D1 and D2.

mabee it is a bit of ambitious code for the purpuse, which is to write 2 different register in sequence.

mabee you should just generate 2 write enable signals for each register write,
and then store the data to them ...
ofcourse in your case extra signal will be created to block another write enables.
so mabee if you practice implement this with dff and gates i twill help you brush up your
digital design skills.