reduce undershoot
1> there is a paper about handling damping effect , u can have a look on it... but this is "super difficult" for me, since it need to design more extra circuits to "tackle" the damping effect......
2> if there is no cap, how about the current pass through the Power pmos at final stage ? did u simulate the line/load regulation form 0um to say 100um ? i wondering if this is possible foy PMOS to "operate" when there is no load current provide
3> why you would like to work on without capacitor ? in fact, i also doing on it..but, may be i am not that good/clever on circuit design, it seems to me that without a cap. this is just of "produce paper purpsoe"....in real life.....may be, not that easy for Design For Manacufacting DFM.......................
All are just my feeling on this topic, if there is anythings worng, plz to correct me.....