Oversampling / Skew compensation - VHDL

[The_Dutchman]

Hello,

For my master thesis I'm using a transceiver (fancy serializer) that has a 64-bit wide TXDATA input port that gets serialized from bit 0 to 63 on the rising edge of TXUSERCLK2.
However there is skew between different transceivers (PCB track lengths etc) and I am trying to compensate this skew misalignment by oversampling and placing the right amount of 0's in front of the data.

So e.g. if this is the output of 4 transceivers (started at the same time)
0000000011011001110 (add 0 zeros)
0000001000101010001 (add 2 zeros)
0000010000001010001 (add 3 zeros)
1001011100111111000 (add 8 zeros)

To increase the resolution I also use oversampling, so if the oversamplingfactor is 2 then TXDATA(1) & TXDATA(0) have to stay TXNEEDTOSEND(0) and so on.

I'm really stuck with this because I have written code (attachment) that does what I need, but does not synthesize and using a switch statement will be very very very much lines of code. I'm thinking I'm just overlooking the simple solution here, could someone maybe help a hand ?

Thanks in advance,

 

[ro9ty]

Hi from the synthesis POV i can also say that this code would not be synthesizable. For a quick analysis as to the other best possible option you could use a linting tool if you have like spyglass. This construct would show an error and you would know how best to implement it.

 

[TrickyDicky]

Hi from the synthesis POV i can also say that this code would not be synthesizable. For a quick analysis as to the other best possible option you could use a linting tool if you have like spyglass. This construct would show an error and you would know how best to implement it.

It looks ok to me...

 

[std_match]

The synthesis tool probably doesn't like to have vector ranges defined by variables or signals:

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Code VHDL - [expand]
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TXDATAOVERSAMPLED(upindex downto lowindex) := (others => '0');
...
TXDATA <= TXDATAOVERSAMPLED(oindex+63 downto oindex);

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