Overflow of multi adders in VHDL

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positron90

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I am confusing how to take care of overflow in multilevel adder in VHDL. Supposing we have 3 adders, outputs of two adders are inputs of the last one, and the output of the last adder is latched and fed back to the first adder. Inputs of the two first adder are 8-bit STD_LOGIC_VECTOR. After the first operation, It may result in a 9-bit output, and then 10-bit output in the last adder. So how can I get it back to the first one.
Thanks so much!
Sorry, my English is not good.

---------- Post added at 11:14 ---------- Previous post was at 10:42 ----------

helps me :-|
 

Obviously, you can only feed back 8 bits of the result. You have to decide about the intended adder behaviour. It can be either wrap around (simply ignoring the two most significant bits) or saturation, limiting the result to 255 (decimal).
 

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