Unfortunately, I just found out that the Xilinx FIFO generator is limited to (no more than) 8:1 ratio when an asymmetric width FIFO is implemented.
I can design a wrapper around a 1:1 ratio FIFO and achieve the same functionality with an FSM and a shift register - but before I do so, I'd like to consult the forum...
Have you come across this limitation ?
How did you solve it ?
The shift register design doesn't sound that bad. The two design concerns will be how the flags are used as well as the mode of the FIFO. This is even more true if you need additional fabric registers for timing purposes anyways.
The shift register design doesn't sound that bad. The two design concerns will be how the flags are used as well as the mode of the FIFO. This is even more true if you need additional fabric registers for timing purposes anyways.
10 hours passed since I found out about the 1:8 limitation - and I'm still angry.
With Xilinx's IP's not being very convenient for manual editing https://www.edaboard.com/showthread.php?t=373748
It seems like I'll have to design a wrapper around every different implementation of the 1:1 "mother FIFO".
This is really really annoying!
I think you get better answers here than on the Xilinx forum. Even though they are the vendors of your design.
I remember the pain I suffered when trying to use asymmetrical microsemi fifo's with diff clock for read and write.
A cascade/parallel of 1:x fifos could be used, but again you'd need logic to collect the word before feeding it onto the next fifo/stage. I wouldn't imagine this to be portable between vendors. Whereas the shift register and creating word before fifo will be portable.