lien0205
Newbie level 5
What is the concept of overclock with clock gap?
I have an example which could explain my problem more precisely:
the input signal width to my block is 16bits @sys16_clk; the 16 bits vectors will be concatenated to a 66 bits vector @ sys16_clk. It's impossible to do that because the throughput is 66/16 times than the input. However, I have only one clock domain(sys16_clk).
The idea is to 'slow' sys16_clk into sys66_clk by using something called clock gap. So my question is what does it mean by 'clock gap' and how to achieve that in circuit?
Thank you.
I have an example which could explain my problem more precisely:
the input signal width to my block is 16bits @sys16_clk; the 16 bits vectors will be concatenated to a 66 bits vector @ sys16_clk. It's impossible to do that because the throughput is 66/16 times than the input. However, I have only one clock domain(sys16_clk).
The idea is to 'slow' sys16_clk into sys66_clk by using something called clock gap. So my question is what does it mean by 'clock gap' and how to achieve that in circuit?
Thank you.