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# Output variables sequentially?

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#### random_duck

##### Newbie level 4
Ok, so assume I have two or more variables like this:

shared variable char_one : std_logic_vector(7 downto 0); -- ASCII character one.
shared variable char_two : std_logic_vector(7 downto 0); -- ASCII character two.
...
...

I am trying to figure out, how I can possibly output the values of these variables on an output pin (signal, std_logic_vector(7:0)) sequentially, one after the other, provided a certain signal is currently high.

I guess a FIFO buffer might work, but surely there must be a simpler way? I am a beginner to VHDL, but truly puzzled at the moment.

Thanks. :smile:

#### rahdirs

Hi,

You can implement a simple counter & output the next shared variable after each increment of the counter using a case statement or something similar.
This would be hard coding & btw how many shared variables do you have ?

On the other hand why do you think FIFO buffer is difficult ?If you are using Xilinx ISE/Vivado they have a FIFO ip core which you can readily implement.

#### TrickyDicky

Why are you using shared variables? There is absolutely no reason to use them in synthesisable vhdl. I worry you're thinking like a software programmer and not like a hardware designer.

#### random_duck

##### Newbie level 4
Thanks for the replies.

Hi,

You can implement a simple counter & output the next shared variable after each increment of the counter using a case statement or something similar.
This would be hard coding & btw how many shared variables do you have ?

On the other hand why do you think FIFO buffer is difficult ?If you are using Xilinx ISE/Vivado they have a FIFO ip core which you can readily implement.

Hmm, counter might be a wise option. Thanks for the suggestion. Some questions:

* So would the counter count for a fixed number of clock cycles, and then trigger a flag once it 'fills up'?

* Would I have a separate process for the counter, and check the value of the counter flag inside the other process I am using?

I only need two variables at the moment, but I might need more in the future.

Why are you using shared variables? There is absolutely no reason to use them in synthesisable vhdl. I worry you're thinking like a software programmer and not like a hardware designer.

Hmm, OK maybe I shouldn't use them from now on then, I can see that it may turn into a 'bad' habit.

As an additional question: Is it easy to take it a step further, and output pre-defined 'strings'? By string, I mean a sequence of pre-defined numbers...

Thanks again.

#### rahdirs

Thanks for the replies.
Hmm, counter might be a wise option. Thanks for the suggestion. Some questions:
* So would the counter count for a fixed number of clock cycles, and then trigger a flag once it 'fills up'?
* Would I have a separate process for the counter, and check the value of the counter flag inside the other process I am using?
I only need two variables at the moment, but I might need more in the future.
Thanks again.
Say you have five variables,instead of the two you have.
Write a counter module,output of the counter is an integer.(counter counting from 0 to 3 & then resets to 0,incrementing at every clk cycle).
You don't need to wait till counter counts to max value,makes sense ?

Instantiate the counter in your top module & write a case statement.

Int_Count is counter o/p & Z is your top module o/p

Code Snippet of sequentially assigning your o/p
Code:
process(Int_Count,clk,char_one,char_two,char_three,char_four)
begin
case Int_Count is
when 0      =>  Z  <= char_one;
when 1  =>  Z <= char_two;
when 2  =>  Z <= char_three;
when 3  =>  Z <= char_four;
when others =>  Z <= (OTHERS => '0');
end case;
end process;

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