Output Pins stuck at VCC? Code issue?

[digi001]

I am looking to latch an enable signal only when my fpga is addressed correctly and recieves a specific code. But i am having issues getting this to work. Is my code correct?

Here is my verilog:



module fpga_enable_version(xint,cs,rd,we,address,enable_o ut);

input cs;
input rd;
input we;
input [3:0]address;
output enable_out;
inout [15:0]xint;

reg enable_reg;

initial
begin
enable_reg=1'b0;
end

assign enable_out = enable_reg;


always @ (*)
begin
if (address==4'b0010 && cs==0 && we==0 && xint==16'b0000111100001111)
begin
enable_reg <= 1;
end
end


endmodule

 

[sameh_yassin99]

Hi there,
I used Altera Quartus to draw the schematicd for your code. It looks as follows.

---------- Post added at 10:19 ---------- Previous post was at 10:13 ----------

You should change your code to have some sequential element.

initial
begin
    enable_reg=1'b0;
end

assign enable_out = enable_reg;

always @ (negedge cs)
begin
   if (address==4'b0010 )
   begin
     enable_reg <= 1;
   end
end

---------- Post added at 10:22 ---------- Previous post was at 10:19 ----------

and the output will be

 

[digi001]

Yes! This is exactly what I tried yesterday and it works.

But i'm still not sure why I cant just have asynchronous logic that is triggered off the WRITE signal going low.

 

[TrickyDicky]

you can. But in your code enable_out goes to one and then never changes to zero. Hence why the output is always one.

 

[digi001]

But that is the functionality of a latch. Upon a certain condition...it goes to 1 and then never again goes to zero, except maybe a reset or something.

---------- Post added at 10:07 ---------- Previous post was at 10:06 ----------

sameh, how did you generate those pictures from Quartus?

 

[TrickyDicky]

that is the RTL viewer.

 

[sameh_yassin99]

Tools -> Netlist viewers -> RTL viewer

Have fun

 

[FvM]

Apart from the question if the design makes much sense, we should clarify why the synchronous implementation can be synthesiszed but the asynchronous can't. It's in fact not obvious at first sight. In my opinion, it has to do with the fact that the initial block can be only synthesized for synchronous logic respectively hardware registers.

It's implemented as power on reset of the FPGA. But the asynchronous latch can be only implemented as logic loop and in this case hasn't access to the interna POR signal. If you add however an explicite reset signal and wire it to the latch, then the latch can be synthesized.

if (reset ==1'b1)
  enable_reg <= 0;
else if (address==4'b0010 && cs==0 && we==0 && xint==16'b0000111100001111)
  enable_reg <= 1;

As an additional comment, IEEE Std 1364.1 that tries to standardize the synthesizable subset of the Verilog language tells:

The initial statement shall be supported only for ROM modeling as described in 5.6.2. It shall be ignored in all other contexts.

In so far the present practice to implement initial blocks as register power-up state is not complying to the new standard. It will be possibly kept as an option by those synthesis tools that supported it previously. But it emphasizes that you should better use explicite reset conditions.

 

[mrflibble]

You bring up a good point FvM. Does this also apply to register initialization?

I use a lot of this:

reg enable_reg = 0;

That way, after configuration I'm sure of the register state, without having to explicitely mess with power on reset signals. Your post now has me wondering if that's a good way to go about it. It seem to work just fine with ISE 10.x through 13.x so far (both synthesis and simulation), but maybe I am missing some of the finer details here...

 

[FvM]

Initializers for registers work fine in most tools as far as I'm aware of. They surely work in Altera Quartus and I think Xilinx ISE as well, an dthere should be no functional difference between initial blocks and register definitions with initial value. I quoted 1364-1 mainly to show, that's it's not an obvious feature in synthesized logic. If tool designers intend to achieve compliance with IEEE 1364-1, they'll possibly provide a virtual POR signal that can be used to perform register resets. For th etime being, everything can be expected to work as we're knownt to.