Output CLOCK signal in DFT question

[horzonbluz]

Hi, my friends.
Now i have three submodules in my design.These subdesign divide my system clock signal and output the generated clock signals to outside of chip. In DFT flow,
how we handle these output clock signals? Do we need insert scan chain in this kind of submodule?

 

[santhosh007]

Hi, my friends.
Now i have three submodules in my design.These subdesign divide my system clock signal and output the generated clock signals to outside of chip. In DFT flow,
how we handle these output clock signals? Do we need insert scan chain in this kind of submodule?

If you are doing the scan insertion at the chip level, you need add a bypass mux to bypass the generated clocks during the Test mode.

or If you are inserting the scan chains at the sub modules level, then define the generated clock as scan clock(bcoz the internal clock genration is outside submodules) while inserting at the chip level use a bypass mux to bypass the clock during test mode and define your system clock as scan clock at the chip level

 

[horzonbluz]

Hi, friend. I don't what you mean. All you have said is a normal DFT flow.
My these submodules are clock generated modules. They generated output clock signals to outside of my chip. I want to know how to handle these submodules? If we need insert scan chain in this kind module? In DFT flow, how to handle the output clock signals?

 

[sunilbudumuru]

Hello Friend,

My suggestion is just dont insert scan for these sub-modules.
You can have more info here.


Sunil Budumuru

 

[horzonbluz]

sunilbudumuru, my friend.
Thanks for your help. I will try this flow as you have said.