LDOs operate the pass FET in linear region -when low
supply headroom- but this is not to be assumed - you
have to design for the low line, high load corner (the
LDO case) but also its opposite (high line, low / no
load) and there you may well be in saturation. The
need to swing across that space is probably the biggest
design challenge, especially with regard to compensation
and step-load response, with a highly variable final stage
gain thrown in for good measure.