OTA Design for pipeline ADC

[suhas_shiv]

Hi all,

I am designing an OTA/opamp fora 8-bit pipeline ADC(40MHz sampling). What is the fu(unity frequency) that I must aim for? What architecture is usually preferred for this application?
Thanks.

Added after 1 hours 13 minutes:

Forgot to mention that this ADC would be for a video application.

 

[holddreams]

《CMOS: Mixed-Signal Circuit Design》
equations:
(34.43) --------fu≥0.22(N+1)fclk

 

[wael_wael]

《CMOS: Mixed-Signal Circuit Design》
equations:
(34.43) --------fu≥0.22(N+1)fclk

hi
could you tell me name of the outher
thanx

 

[sachinagg77]

The OTA specifications for Unity Gain Frequency will depend on the following factors:

1. Resolution Required
2. Settling Time Requirements
3. Feedback Factor [this depends on the configuration used]

 

[holddreams]

Backer

quote="wael_wael"]

《CMOS: Mixed-Signal Circuit Design》
equations:
(34.43) --------fu≥0.22(N+1)fclk

hi
could you tell me name of the outher
thanx[/quote]

 

[suhas_shiv]

I think the author is Baker and Boyce.

Added after 18 seconds:

or just Baker.

 

[analoger]

Folded cascode can acheive