[SOLVED] ORing even & odd bits of a vector

rahdirs · Aug 26, 2017

Suppose, I have a vector:

Code Verilog - [expand]
1
logic [127:0] x; // one hot

I want to OR the even bits & odd bits seperately, as in x_even = x[0] | x[2] | x[4] | ...... x[126] & similarly for the odd bits. I tried the following but it's pointing a syntax error at |=

Code Verilog - [expand]
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generate
  for (i=0;i<64;i++) begin
    x_even |= x[2*i];
    x_odd  |= x[2*i+1];
  end
endgenerate

Regards,
rahdirs

vGoodtimes · Aug 26, 2017

Code:

  odd = |((64){2'b01} & x);
  even  = |((64){2'b10} & x);

I'm not sure if Verilog supports |=. SystemVerilog does.

In either case, this probably can't be done in a generate due to multiple assignments to the same net.

[SOLVED] ORing even & odd bits of a vector

rahdirs

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vGoodtimes

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rahdirs

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Code Verilog - [expand]
1 2 3 4 5 6	generate for (i=0;i<64;i++) begin x_even \|= x[2i]; x_odd \|= x[2i+1]; end endgenerate

[SOLVED] ORing even & odd bits of a vector

rahdirs

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vGoodtimes

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