circuit_hunter
Junior Member level 3
Hi
I am trying to understand an NMOS circuit whose ID-VDS characteristics as found using default NMOS model in LTspice is as follows:
![Fig1.PNG Fig1.PNG](https://www.edaboard.com/data/attachments/69/69127-23f23efd4a0ea3fd90719d925f0c8c29.jpg)
![Fig2.PNG Fig2.PNG](https://www.edaboard.com/data/attachments/69/69128-1d1df04d6cae417c70f10744fb71c974.jpg)
I know that a mosfet has a transconductive behavior- vgs produces ids and that with external circuit sets the vds; ignoring channel length modulation. But, can a current injected into drain produce vds? To know that, I have simulated the following circuits where I use abnormally high inductors to stop signal flow to the drain resistor R1 :
Case 1: Ideal Current source:
![Fig3.PNG Fig3.PNG](https://www.edaboard.com/data/attachments/69/69129-70cc16462a7e4eb697a13da131e696b8.jpg)
![Fig4.PNG Fig4.PNG](https://www.edaboard.com/data/attachments/69/69130-b56dfa9583db7b79c1039400d15f68ab.jpg)
and Case 2: a current source with some source resistance:
![Fig5.PNG Fig5.PNG](https://www.edaboard.com/data/attachments/69/69131-d1936ae8991c65a5e0d15d8f4a4199d7.jpg)
![Fig6.PNG Fig6.PNG](https://www.edaboard.com/data/attachments/69/69132-2fcc248c2a5638ffb0330b09d17e0ad7.jpg)
I have been trying to explain the following question to myself, but I am not arriving at convincing answers:
(1) For case 1, why the ids =Id(M1) has a DC shift? Its swing is total swing of the injected current, but why?
(2) As for the voltage across R1, V(d_bias), it is just because of the average current that flows to R1, right?
(3) For case 2, why the ids is clipped? This time, the current flows into the source resistor R2 for positive cycle and into the NMOS for the negative cycle.
Somehow it looks like positive current cannot flow into these configurations. Please help me explain these questions.
Thanks.
I am trying to understand an NMOS circuit whose ID-VDS characteristics as found using default NMOS model in LTspice is as follows:
![Fig1.PNG Fig1.PNG](https://www.edaboard.com/data/attachments/69/69127-23f23efd4a0ea3fd90719d925f0c8c29.jpg)
![Fig2.PNG Fig2.PNG](https://www.edaboard.com/data/attachments/69/69128-1d1df04d6cae417c70f10744fb71c974.jpg)
I know that a mosfet has a transconductive behavior- vgs produces ids and that with external circuit sets the vds; ignoring channel length modulation. But, can a current injected into drain produce vds? To know that, I have simulated the following circuits where I use abnormally high inductors to stop signal flow to the drain resistor R1 :
Case 1: Ideal Current source:
![Fig3.PNG Fig3.PNG](https://www.edaboard.com/data/attachments/69/69129-70cc16462a7e4eb697a13da131e696b8.jpg)
![Fig4.PNG Fig4.PNG](https://www.edaboard.com/data/attachments/69/69130-b56dfa9583db7b79c1039400d15f68ab.jpg)
and Case 2: a current source with some source resistance:
![Fig5.PNG Fig5.PNG](https://www.edaboard.com/data/attachments/69/69131-d1936ae8991c65a5e0d15d8f4a4199d7.jpg)
![Fig6.PNG Fig6.PNG](https://www.edaboard.com/data/attachments/69/69132-2fcc248c2a5638ffb0330b09d17e0ad7.jpg)
I have been trying to explain the following question to myself, but I am not arriving at convincing answers:
(1) For case 1, why the ids =Id(M1) has a DC shift? Its swing is total swing of the injected current, but why?
(2) As for the voltage across R1, V(d_bias), it is just because of the average current that flows to R1, right?
(3) For case 2, why the ids is clipped? This time, the current flows into the source resistor R2 for positive cycle and into the NMOS for the negative cycle.
Somehow it looks like positive current cannot flow into these configurations. Please help me explain these questions.
Thanks.