Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

operation of an NMOS circuit

Status
Not open for further replies.

circuit_hunter

Junior Member level 3
Joined
Jan 8, 2017
Messages
25
Helped
1
Reputation
2
Reaction score
1
Trophy points
3
Activity points
344
Hi

I am trying to understand an NMOS circuit whose ID-VDS characteristics as found using default NMOS model in LTspice is as follows:

Fig1.PNGFig2.PNG

I know that a mosfet has a transconductive behavior- vgs produces ids and that with external circuit sets the vds; ignoring channel length modulation. But, can a current injected into drain produce vds? To know that, I have simulated the following circuits where I use abnormally high inductors to stop signal flow to the drain resistor R1 :

Case 1: Ideal Current source:

Fig3.PNGFig4.PNG

and Case 2: a current source with some source resistance:

Fig5.PNGFig6.PNG

I have been trying to explain the following question to myself, but I am not arriving at convincing answers:

(1) For case 1, why the ids =Id(M1) has a DC shift? Its swing is total swing of the injected current, but why?
(2) As for the voltage across R1, V(d_bias), it is just because of the average current that flows to R1, right?
(3) For case 2, why the ids is clipped? This time, the current flows into the source resistor R2 for positive cycle and into the NMOS for the negative cycle.

Somehow it looks like positive current cannot flow into these configurations. Please help me explain these questions.

Thanks.
 

The MOSFET with G=S=B=gnd! will change behavior
if you try to drive the drain negative. Presuming the
body diodes are well modeled, you will light up the
D-B diode when you go much below ground.

When you try to impose more current than the FET
channel "wants", it has to go elsewhere (like into your
shunt resistor). If you probe the FET drain current
you will see only part of what you force, if there is
another way out for the forced current. FET models
tend to not have good breakdown behavior, if any
at all.

The simple classical formulae are valid over limited
regions of operation. When you push the FET past
these, the "models" cease to apply and then things
"don't make sense".
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top