operating region of pass element in LDO

[anhnha]

I am really confused. What is the operating region of pass element in LDO (Low Dropout Linear Regulator)?
I see a lot of documents saying that it operates in linear mode. However, in this page, at slide 37, the author considered the power MOS operating in saturation for that calculation.
Could you please explain?

 

[SIDDHARTHA HAZRA]

I am really confused. What is the operating region of pass element in LDO (Low Dropout Linear Regulator)?
I see a lot of documents saying that it operates in linear mode. However, in this page, at slide 37, the author considered the power MOS operating in saturation for that calculation.
Could you please explain?

Depending on the the drop out voltage and load current variation a Power FET can operate in either linear or saturation.

Considering a low drop out: Say supply is 2V and Output required is 1.8V so the VSD of the Power FET is 200mV. Now take two load current spec. 10mA - 1mA, and the other 100mA - 1mA.

In the later case the VG variation will be huge as the load range is huge. So the VG in the later case is likely to vary from very low voltage (100s of mV from VSS) in full load to very high voltage (100mV lower than VDD) when load is low. So at full load the VSG is almost = VDD (a few 100mV here and there). but the VDS is only 200mV . So VSG -VTH > VSD which will make the Power FET operate in linear region. But if the load current range is small then even with a small drop out the VG can be adjusted to such a value that the Power FET operates in saturation.

Hope this helps ...

 

[Audioguru]

The word "saturation" is true for a bipolar transistor. When it is saturated then it is turned on very hard so that its collector-emitter voltage is low. When it is linear then it is an amplifier with plenty of collector-emitter voltage.

But a Mosfet is the opposite. When it is turned on very hard with a low drain-source voltage then it is said to be "triode", "ohmic" and "linear". It is said to be "saturated or "active" when it is a linear amplifier with plenty of drain-source voltage.

Read all about it in Google.

 

[subhash_chevella]

Hi all,

Could any one pls explain me, how to derive Error Amplifier specifications from the given LDO specifications?

I have below specifications:
Vin : 2.7-3.3V
Vldo: 2.5
Iload: 0-40mA
Quiescent Current: <50uA
Settling time: 100uS
Line/Load Reg variation: <1%

From these, how can I determine the bandwidth, gain, 3db freq of the error amplifier?

regards,
Subhash C

 

[SIDDHARTHA HAZRA]

Hi all,
Could any one pls explain me, how to derive Error Amplifier specifications from the given LDO specifications?

I have below specifications:
Vin : 2.7-3.3V
Vldo: 2.5
Iload: 0-40mA
Quiescent Current: <50uA
Settling time: 100uS
Line/Load Reg variation: <1%

From these, how can I determine the bandwidth, gain, 3db freq of the error amplifier?
regards,
Subhash C

Hi Subhash C,

Please create a separate post for your question. This thread is to discuss anhnha's questions (who initiated the post). It is every bodies responsibility to keep the tread clean.
Creating a post of your own will expose your post to every body and you can get better answers.

 

[anhnha]

Thank you, SIDDHARTHA HAZRA and Audioguru.

As you said, when load current is large => VSG is large => VG is small.
I don't really understand how LDO maintains constant output voltage as power MOS operating in saturation.
With power MOS it makes sense.
Assuming that Rload decreases => Iload increases => Vout decreases => feedback voltage Vfeedback decreases =>
Vout of error amplifier decreases => VG decreases => power MOS conducts more (its resistance decreases) => Vout (of LDO) increases.

How to understand how power MOS help maintain output voltage of LDO while it works in saturation region?
Thanks.

 

[Audioguru]

We do not know what you are talking about since I don't think any IC LDO voltage regulator has a Mosfet at its output.
In your first post you said, "in this page, at slide 37" but you did not attach it to your post.

 

[D.A.(Tony)Stewart]

A MOSFET is a Voltage controlled current source above threshold (albeit very nonlinear one) which is limited by the current at saturation voltage or commonly called the RdsON which limits the current it can pass based on in-out offset. So it only operates in saturation if the input supply drops down to saturation at max current. There lies your LDO offset limit based on available voltage to drive the gate and current to prevent saturation of RdsON.

Back to your questions;
Vin : 2.7-3.3V
Vldo: 2.5
Iload: 0-40mA
Therefore RdsON must be < 0.2V/0.04mA = 50 Ohms at available Vgs.(worst case)
Quiescent Current: <50uA
Settling time: 100uS
Line/Load Reg variation: <1%

Line regulation depends on comparator loop gain and band gap stability.
Load regulation depends on LDO output impedance. Since we dont know if load is non-linear (eg LED) lets assume resistive step load 2.5V/0.04A = 62.5 Ohm The output impedance of the LDO is not the RdsON but the RdsOn/loopgain. In order to satisfy 1% load regulation the source impedance must be < 1% Step Load or < 0.6 Ohm. The achieve this the op amp inside the LDO must have a loop gain of >100 to reduce RdsON to < 0.5 Ohm. Too much gain will reduce bandwidth of step response time and load capacitance must have some finite ESR for these types of feedback loops to be stable, or else a minimum pre-load. Details of control theory left out.

From these, how can I determine the bandwidth, gain, 3db freq of the error amplifier?
Too much gain will reduce bandwidth of step response time and load capacitance must have some finite ESR for these types of feedback loops to be stable, or else a minimum pre-load. Details of control theory left out. Without specs of each part or a test, you can't determine rise time ( which depends on load capacitance and RdsON etc) or bandwidth. Since the amplifier is unpolar drive, ( active pull up only) , the step response will be different in each direction.

 

[SIDDHARTHA HAZRA]

How to understand how power MOS help maintain output voltage of LDO while it works in saturation region?
Thanks.

The Vout node or the output of the LDO is loop controlled. By loop controlled it means that if the loop has sufficient gain (and assuming its stable) the the VFB (feedback node) is equal to the VREF (reference voltage). Two input of the error amplifier will be same. Now if VFB is VREF then the lower resistance R2 in the feed back network (i.e. the R2 connected from VFB to ground) will draw VFB / R2 = VREF/R2 amount of current (Ohms Law).
The same amount of current will flow through the upper resistance R1 (R1 connected between Vout and VFB).
Now by ohms law again Vout - VFB = I * R1 = VREF* R1/R2
=> Vout - VREF = VREF * R1 /R2
=> Vout = VREF (1 + R1/R2) So Vout is no where related to MOSFET. It is just the loop that maintains the voltage. So even if your power FET is in saturation loop will ensure that Vout is at its expected value if loop has sufficient gain and it is stable.

Hope this helps ....

 

[jony130]

How to understand how power MOS help maintain output voltage of LDO while it works in saturation region?
Thanks.

Can you build a CS amplifier that his drain voltage (VD) is equal to 0.5Vdd or 2/3Vdd ??
In which region MOSFET is operating? In saturation ? So how it is possible if MOS work as a VCCS?
Also notice that in your LDO regulator your MOS (series pass element) work as a CE amplifier.

 

[anhnha]

Can you build a CS amplifier that his drain voltage (VD) is equal to 0.5Vdd or 2/3Vdd ??
In which region MOSFET is operating? In saturation ? So how it is possible if MOS work as a VCCS?
Also notice that in your LDO regulator your MOS (series pass element) work as a CE amplifier.

Hi, Jony.

I am not sure what you meant to say.
In that case, Vsd = Vdd - 0.5Vdd = 0.5Vdd.
I don't know which region the MOSFET operates but when Vsd decreases, the MOSFET should go into triode region.
Do you mean that the MOSFET should be in triode region?
What do you think about the calculation of pass transistor in page 37 of this slide?