Hi
if you have a complex design, which operating on high frequency , some signals could not have enough time to get from one trigger to another, and such situations could cause metastability or wrong signals on another trigger next clock. Use period constraint to analyze max operating frequency, if after place and route ise shows errors, so your design perhaps will not on such period of clock. If it happend you should manually place components, route some critical paths , use constraints to increase performance of your design, such method requires some experiance from engineer.