You might be able to make a cascode open-drain stage
if you have a HV well or a SOI tub to put the guard NMOS
into. Tie its gate to VDD, source to the "master" switch
NMOS below, drain is the "open collector" output.
But plain cheap JI technology would still leave you with
Vdb=7V and this isn't going to fly, most likely. There's
also the challenge of ESD protection of a pin that's
supposed to not break down below 7V.
Many CMOS flows will let you make (whether or not
the rules allow) LDMOS devices. Like "good ol' C5"
has, I think, 12V-ish LDMOS devices either in the
main flow or as a few-mask "module", TowerJazz
CA18 has 12, 20 and 40V LDMOS in its 1.8/3.3
and 1.8/5V flows, etc.