OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margin

[ryanlee8414]

There is a weird problem I can't explain.
First, I design an opamp that the Open-Loop PM is around 5 degree on purpose.
Then, this opamp is connected like a unity-gain buffer and a pulse is given at input.
There is NO RINGING , No OVERSHOOT/UNDERSHOOT at output and it is very smooth just like PM > 60 .
I guess there exists some non-linearity between output-stage and input-pairs.
Does output impedance and input capacitance make this unity-gain buffer become stable ?

 

[LvW]

Re: OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margi

I don't think so because these parasitic values are also effective during open loop simulations - if these simulations are performed correctly!!!.
It would be best to show the circuit under test as well as the open-loop simulation arrangement.

 

[ryanlee8414]

Re: OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margi

The attached file is the simulation results.

I've found something interesting.

When the opamp is compensated by Miller R&C , the open-loop AC sim doesn't match close-loop step response , shown in the attached file.

However , while only using Miller C without R , the open-loop AC sim matches closed-loop step response which means PM=5 at open-loop and it does ring at step response.

 

[LvW]

Re: OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margi

I don't understand the first test circuit.
Do you intend to simulate the open loop response? Why feedback resistors with what values? Different values for ac and dc ? Which amount of capacitive loading?

 

[ryanlee8414]

Re: OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margi

In Hspice Netlist

RF Vo V- DC=1u AC=100G # DC R=1u ohm ; AC R=100G ohm
RI V- Vref DC=100G AC=1u # AC R=1u ohm ; DC R=100G ohm


that means it only feedback DC operating point to V- instead of AC.
It is similar to use RC low-pass-filter or LC low-pass-filter to feed DC back.

Any idea about the simulation results ?

Added after 2 minutes:

one more thing , the capacitive load is 10pF

 

[LvW]

Re: OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margi

I am not familiar with HSpice. Therefore my question:
Is it really possible in HSpice to use a resistor with different values - depending on the kind of analysis?

I understand that you have problems to match results from ac and tran analyses, right?

You have mentioned that you - purposely - have designed a PM of only 5 deg.
Are you really sure about that value (because it is rather close to the critical limit).
More than that, you cannot (blindly) trust results from ac analyses because sometimes stability is indicated (PM positive), whereas under real conditions the circuit is unstable. In the first picture there is at high frequencies (10 MHz?) a peak with a phase excursion which seems to be critical.
On the other hand, perhaps it must be attributet to the non-ideal open-loop test arrangement with a capacitive load (try to remove it). To be honest, I don't trust your scheme with the 100Gohms resistors.
I recommend to use one of the classical loop gain simulation arrangements.
If you are interested in the unity gain configuration only, put a resistor (100k) between output and (-) input and ground the (-) input with a large capacitor (1...100 Farad).
Regards and good luck.
LvW