Re: OPAMP's Open-Loop Phase Margin vs Close-Loop Phase Margi
I am not familiar with HSpice. Therefore my question:
Is it really possible in HSpice to use a resistor with different values - depending on the kind of analysis?
I understand that you have problems to match results from ac and tran analyses, right?
You have mentioned that you - purposely - have designed a PM of only 5 deg.
Are you really sure about that value (because it is rather close to the critical limit).
More than that, you cannot (blindly) trust results from ac analyses because sometimes stability is indicated (PM positive), whereas under real conditions the circuit is unstable. In the first picture there is at high frequencies (10 MHz?) a peak with a phase excursion which seems to be critical.
On the other hand, perhaps it must be attributet to the non-ideal open-loop test arrangement with a capacitive load (try to remove it). To be honest, I don't trust your scheme with the 100Gohms resistors.
I recommend to use one of the classical loop gain simulation arrangements.
If you are interested in the unity gain configuration only, put a resistor (100k) between output and (-) input and ground the (-) input with a large capacitor (1...100 Farad).
Regards and good luck.
LvW