OpAmp design for SC-integrator

[woodrave]

op amp integrator design

Hello,

for a school project, we have to design an OpAmp for a switched-capacitor integrator. The goal is to design the OpAmp for the first integrator (see picture) with the following constraints:

-clock frequency: 50 MHz
-3.3V
-Choose Vcm and Vcm,in as good as possible

I'm not looking for someone who gives me a finished circuit, but rather for some directions on how to start.
I already did some research, and found that your GBWP should at least be 10 times fclock, so that would be 500 MHz here. Is that a good choise?
For the voltage Vcm,in , I suspect it to be as low as possible. Depending on the circuit this would be something like 2*Vdsat. And for Vcm: half the Vdd voltage: 1.65 V. This allows a maximal swing.

Furthermore, I'm not sure what the load capacity is for the first integrator. I calculated 4.5 pF, but I'm not sure of that.

And for the topology, I suggest it would be good to use an OTA, since the load is completely capacitive. But I'll probably need a second stage to obtain a good gain...

Can someone tell me if I'm thinking in the good direction here, or is this all completely wrong?

cheers,

Bert

 

[shainky]

sc integrator

What i feel is a simple op amp can be made using a differential amplifier circuit too. Use a current mirror to act as a constant current source. Bias your transistors, Obtain gain value. Check for the stability of the system. Get gain margin , phase margin. Get the unity buffer characters. If everything is satisfactory then use frequency compensation to increase the bandwidth so as to obtain an optimum gain bandwidth product.

 

[woodrave]

integrator design

Hey, thank you for you answer.
I already made something (see picture). Could this work? The dimensioning is not right yet, so I haven't tested this circuit.
But I'm a bit unsure about the specs. What exactly should I do for the fact that it's an SC-integrator. Is this just important in the beginning (capacitive load, slew-rate,...) or are there other special things that need to be done for such an OpAmp?
How much should the GBWP be? And how much is the capacitive load?

cheers,

Bert

 

[shainky]

project on opamp as integrator

The circuit should work. The W/L variation can also be done in simple multiples of 50/2 or so.

For a 1st order design, you can take the parameters as:
1)SR = 10 V/usec
2)Av = 5000 V/V
3)GB = 5 MHz
4)CL = 10 pF
5)Pdiss < 0.3 mWatt
6)ICMR+ = 1.5 Volt
7)ICMR- = 0.2 Volt

 

[woodrave]

capacitive load integrator

Thanks for the reaction shainky!
I was just wondering if the GBWP of 5MHz is enough for this circuit? I didn't have the time to try it out yet, but I'll do it as soon as possible, and post the results.

cheers,

Bert

 

[haoshs]

I also have the same question: "Is the the GBWP of 5MHz enough for the 50MHz sample frequency? ". In my opinion, the GBWP should be at least 5 times fclock, that is 25MHz.