OPA in sample-hold circuitry

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lunren

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Dear all,
I have been designing a sample-hold circuitry for ADC (12 bits). The input voltage is from 0V to Vref. The input pair of the OPA is PMOS. But when the input voltage is 0, the output of the follower is 20mV. Could somebody give some comments on this issue? How can I reduce the offset of the OPA as low as possible? What are key specifications of the OPA in sample-hold ciruitry? Any comments or papers about the OPA (or rail to rail opa) in somple-hold circuitry are welcome.
 

Did you check the proper biases? Kindly send us the results of your simulations where you have characterized the amp for offset. 20 mV is a big error.
 

Vamsi Mocherla said:
Did you check the proper biases? Kindly send us the results of your simulations where you have characterized the amp for offset. 20 mV is a big error.
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Hi, Vamsi Mocherla,

It is just a follower with 0 input, the output is 20mV. I think this 20mV includes offset of the OPA and charge injection. Do you have any idea to reduce the offset of the OPA.
 

I think that this offset is due to the charge injection errors. Make sure that your sample and hold circuit has an input/output offset cancellation plan. I still think that your opamp is fine. Did you try to put in the continous time domain and check the offset of your amplifier.
 

What's your meaning by "continous time domain"? is it equivalent to transient simulation?
 

tricks to reduce offset (input referred + charge injection) used are to use dummy switch to mimimize charge injection from the clock and switched cap based bottom plate sampling to kill the input referred offset. I agree, 20 mV offset for over 10bit converter is bad.
 

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