op amp problem - sudden high input bias current with large signal input

[Colon]

hi guys,

So, I have an opamp circuit that has been having problems when I drive it with a large signal. I have stripped away a lot of the circuit to it's simplest state but the problem remains. What I now have is basically an ac coupled non-inverting stage (using a THS4031 opamp), powered from 24V. The non inverting input is biased with a low terminating resistor (300R in this case, AC coupled to ground with a 10uF cap) to mid rail (voltage produced by a resistive divider). I have removed my usual output load (which was a push pull stage) and replaced it with a 10k resistor to simplify things.

When I have a large input signal (peak voltage approx 20V) the output suddenly distorts massively, while the input bias current increases dramatically, pulling the input DC level down from mid rail by a few volts.

I suspicion was that I nearing the common mode input voltage limit. I have read that going near this limit results in increased input bias current and sudden phase inversion, but I'm at least 2V away from that. What's stranger still is that I attempted to limit the input voltage to 1V below the point at which I see this effect occur, via diodes connected to the appropriate voltages. The waveform clipped early as expected but the problem simply occurred at a lower voltage instead!

Upping the supply to 30V just moved the point at which the problem occurs up to around 24V, far from the rail.

I am really stumped now as to what is going on. Everyone else I work with, some with much more experience than me in opamps, are stuck too. Hoping someone on here has seen this before

Thanks
James

- - - Updated - - -

Is this maybe a case of large signal instability?

 

[monsoon]

Hi
What is the closed loop gain of your non-inverting stage?Just a voltage follower, I believe.

 

[crutschow]

Post the circuit diagram.

 

[Colon]

Ok, here is the stripped down version of the amp that still shows the problem. Yes, I forgot to say, it's unity gain.

Here is the original, because once I fix it, I'll need to keep it working with my full circuit. It's larger though, and I haven't managed to capture it with quite enough details to make out all the component values



The full circuit is nice and stable at low signals, both in simulation and in practise. I have had a read around and I'm pretty sure it is large signal instability causing the problem. it seems the best way to smulate this is through a transient step response. However, the oscillation I think is very low frequency, rather than high. I'm going to have a play with the simulator now and see what comes out.

Thanks for your input
James

 

[BradtheRad]

1.

What is your sinewave generator's impedance? According to your schematic, it sees a load consisting of C2-R2-C10, which might be as low as 300 ohms. This may be causing distortion of your sine wave.

2.

Does the problem occur when the AC input is above 8.4 V nominal? That produces 24 V peak-to-peak. That's the limit you would expect to get from an op amp with a 24V single supply.

 

[Colon]

1.

What is your sinewave generator's impedance? According to your schematic, it sees a load consisting of C2-R2-C10, which might be as low as 300 ohms. This may be causing distortion of your sine wave.

2.

Does the problem occur when the AC input is above 8.4 V nominal? That produces 24 V peak-to-peak. That's the limit you would expect to get from an op amp with a 24V single supply.

Thanks for the reply.
1. Our signal source is 50 ohms but it is actually transformed to a higher impedance of 200 Ohms before the circuit I have attached. the 300Ohms isn't a perfect match but it's still good and gives us a little more signal gain.
2. The problem occurs before this point when the peak voltage is around 20V going into the amplifier (so thats 12V dc bias plus 8V peak on the sine wave). In actual limiting the sine wave to below this (squaring it up effectively) makes the problem worse.

It's worth mentioning also that the distortion doesn't occur if the op amp isn't connected (and we are just driving the termination impedance on it's own), so it's definitely op amp action causing it.

I earlier thought of something that may explain it, but I need to go and check now. I am wondering if there is ringing present on the limited sine wave on the output of the amp, causing it to hit the problem threshold earlier. I have been monitoring the op amp input rather than the output (which is feeding straight back to the inverting input). I'll go and do some tests now...

James

- - - Updated - - -

well, there is next to no ringing on my amp output, which means it is definitely not a case of reaching the common mode input voltage limit on either input pin. Also, if I switch my signal source to output a square wave the problem occurs much earlier. So, I can put a much larger signal into the amp if it is a sine wave.

Also, looking on a spectrum analyser, as I increase the input power there becomes a point when a low frequency oscillation is seen (less than 1kHz). So I definitely have large signal instability. Quite how I fix that, or whether it will solves all my problems, I don't know.

One additional change I have made is add a 12V regulator to produce my bias. This was I have at least 80dB of isolation (at these low frequencies) to rule out any positive feedback through my bias network.

 

[BradtheRad]

Another possibility: Does the input ever peak higher or lower than the supply to the op amp? If so then it might bring out odd behavior. Operating guidelines for IC's commonly advise against this.

Some op amps are known to develop 'output latch up' when their inputs receive a volt level higher or lower than the supply rails. Example, TL082.

There is also the chance that the capacitor charge might swing up or down suddenly due to surges or drains on the supply. Several cycles must go by as they re-gain their balanced volt level.

 

[Colon]

Another possibility: Does the input ever peak higher or lower than the supply to the op amp? If so then it might bring out odd behavior. Operating guidelines for IC's commonly advise against this.

Some op amps are known to develop 'output latch up' when their inputs receive a volt level higher or lower than the supply rails. Example, TL082.

There is also the chance that the capacitor charge might swing up or down suddenly due to surges or drains on the supply. Several cycles must go by as they re-gain their balanced volt level.

So, it wouldn't appear that there are any spikes near to the input common mode limits of the amp. I set a trigger on my scope and at no point did I see a spike.

Something I have just noticed though. The behavior is dependent upon duty cycle. I am using a standard cheap function generator to give me an input signal large enough to cause a problem with the amp. This has a symmetry adjustment. I noticed that the waveform was looking slightly distorted and this was due to the symmetry being slightly no 50/50.

Here is the interesting thing:
1. The effect worsens the more non-symmetric the input waveform.
2. The effect is opposite depending on whether the duty cyles is <50 or <50. <50 and the waveform and associated dc bias point move downwards towards ground as the effect occurs. >50 and the waveform and dc bias move upwards towards the rail.

hmm...

 

[keith1200rs]

I may have missed it but what frequency are you driving it with? It sound like you are using a square wave drive?

Have you looked at the differential input voltage? There is a limit of +/-4V so if you manage to exceed that some parasitic transistors may turn on.

Keith.

 

[Colon]

I may have missed it but what frequency are you driving it with? It sound like you are using a square wave drive?

Have you looked at the differential input voltage? There is a limit of +/-4V so if you manage to exceed that some parasitic transistors may turn on.

Keith.

My range of input frequency is 10kHz to 1.5MHz. For the current tests I just happen to be using 1.5MHz.

I just tested the differential input voltage and actually at the largest signal input it was going above the specified limited. I have added back to back protection diodes across the inputs and it now clamps at +/- 1V so all okay and within limits.

The problem definitely seems to be low frequency stability, at large input signals, caused by my push pull output. The amp is stable (although distorted) at large signals when the push pull output isn't connected.

 

[keith1200rs]

Have you tried adding a resistor in series with the opamp output - maybe 50 or 100 ohms? Your load seems very capacitive which I suspect the opamp won't like.

Keith.

 

[Colon]

Ok, so the output is AC coupled because I don't want to drive dc into my load, and because I am trying to pass between 10kHz and 1.5MHz I need quite a large cap. I could put a series resistor on there but I need to keep noise down so I'm not going to be able to have more than a few tens of ohms. Also, I believe at some point I have tried tried disconnecting the load and output capo and found it made not different unfortunately.

I have just spent quite a while trying to stabilise the amp. The problem is it is only unstable at large signals and I can't simulate this. I have a nice bode plot in spice which seems quite good at telling me how to stabilise for small signals. The simulation shows it to be very stable in this region, with near exactly 180 degrees phase shift in my loop. So, unless there is a sudden phase inversion (like if the input common mode voltage range had been exceeded), it shouldn't be unstable. Yet, I know I am well within common mode and differential limits.

I have a second op amp of choice. I am tempted to go and try this as I am running out of ideas now!

Thanks for everyones input though.

 

[keith1200rs]

I meant a resistor in series with the opamp output - not the final load. The capacitive load I am talking about is the various capacitors you have connected to the opamp output. It is difficult to read the values and the connections are covered by a text box, but I believe they are 10uF and will indirectly be capacitively loading the opamp.

Keith.

 

[Colon]

I meant a resistor in series with the opamp output - not the final load. The capacitive load I am talking about is the various capacitors you have connected to the opamp output. It is difficult to read the values and the connections are covered by a text box, but I believe they are 10uF and will indirectly be capacitively loading the opamp.

Keith.

Ah ok, sorry I misunderstood. I can give it a go for sure. You're right, the values are 10uF. I am using a pair of BJT transistors as a Vbe multiplier and to bias the two output push pull transistors on. Each of these is then bypassed at signal frequencies by 10uF to improve linearity. The two resistors between the push pulls are 10 Ohms to stop thermal runaway. Again, bypassed at signal frequencies.

- - - Updated - - -

Ok, I've tried 50ohms between the amp and push pull stage but this didn't solve the problem unfortunately.

I have also tried out plan B op amp (an AD8099). This is much better and doesn't oscillate. However, it will only take a 12V rail and once I limit the input to stay within the input common mode range, we are unsure if our compression point is too low.

 

[dick_freebird]

Many op amps have cross-clamped inputs and high
differential input voltage will cause high input offset and
input bias current. If the output (through its feedback
network) can't follow IN+ then you'll see the loop come
apart and all kinds of funny.

 

[Colon]

Many op amps have cross-clamped inputs and high
differential input voltage will cause high input offset and
input bias current. If the output (through its feedback
network) can't follow IN+ then you'll see the loop come
apart and all kinds of funny.

Actually, I think you might be onto something there.

This opamp doesn't have clamping diodes to limit the differential input I don't think. And, I was measuring and simulating a differential input voltage outside of the specified limits under large signal conditions. So, I added clamp diodes to limit this. But, either way, the amp isn't going to behave normally, as the conducting diodes would surely mess the input signal up too.

So, I think the solution may be for me to design the circuit with enough loop bandwidth to allow In- to follow In+. This limitatio is coming from my output push-pull and I think the limited factor may be the push pull transistors. They are reasonably high power and don't have a very high Ft. I don't need quite as much power as I initially thought so I will try and find some higher frequency devices for the output.

I'm home now, but I can do some simulations over the weekend and veryify that the differential input voltage is not exceeded.

Thanks!

 

[rohitkhanna]

...So, I have an opamp circuit that has been having problems when I drive it with a large signal. ...

Try referencing your Siggen/ Input source to the virtual GND instead of PS -ve.

Also - if you have diode-clamped the inputs, then why are you trying to drive it with a 20v p-p swing ? Especially without any limitimg resistor in place ? Something is very likely to break.... n'est ce pas ?

 

[kwkam]

your output stage is not fast enough to handle the fast large signal. To improve it, you can improve the output stage and the feedback network. The large input current is due to saturate of the bipolar input stage. For long run, you will destroy the opamp.