Op-amp dominant pole compensation

[sneha rayala]

What happens if you make the o/p pole of the opamp dominant? i.e., we have pole locations in case of miller compensation, let's say we have swapped poles, i.e., the o/p pole is dominant, and then comes the pole at o/p of the first stage, if both are still far apart with a 60-degree phase margin.

What are the pro's and cons?


I have studied in the case of LDO that if you make the o/p pole dominant, then that will have low impedance at o/p and so the better transient response, but I want to understand how and why. Please try to brief this...

 

[LvW]

Question: What is the meaning of "o/p" in the expression "o/p pole of the opamp" ?

 

[Easy peasy]

o/p = output

it is fairly commonly used.

 

[FvM]

Output pole can be utilized for OPs with higher output impedance (OTA) and defined large load capacitance. That's definitely no option for general purpose OP applications. Can be suitable for voltage regulators, as mentioned, and special amplifier applications, e.g. drivers for piezo actuators.

 

[LvW]

o/p = output

it is fairly commonly used.

OK - what do you mean with "output pole of the opamp"?
The opamps transfer function has one or more poles. These poles appear as zeroes of the transfer functions denominator. Thats all we can say.

 

[D.A.(Tony)Stewart]

Dominant pole compensation can be on the input, intermediate stage like most Op Amps or on the output stage as done with MOSFET LDO's where high capacitance exists with low RdsOn.

Ideally, you want maximum BW with >=60 deg phase margin but o/p dominant compensation is extremely load R dependent so there are tradeoffs.

Making the output pole dominant:

• Improves transient response due to low output impedance and fast current delivery.
• Simplifies compensation but requires careful control of load-dependent factors.
• Can reduce PSRR and introduce stability concerns if load variations are not managed.

In LDOs, this design approach is particularly beneficial when fast transient response is critical, as in high-performance voltage regulators for digital systems.

External low ESR caps must have a pole that does not interfere with the dominant pole yet be low enough ESR to improve step transient errors.

• Non-Interfering Pole:
  • The additional pole created by the low ESR capacitor should not interfere with the dominant pole (which ensures stability). If these poles are too close to each other, it could result in degraded phase margin, potentially destabilizing the system.
  • For proper stability, the poles should ideally be well-separated by a sufficient margin (typically 10:1 frequency ratio or more).
• Pole Location:
  • The frequency of the pole formed by the low ESR capacitor should ideally be low enough to improve the transient response, i.e., respond to step load changes quickly.
  • However, if the pole from the low ESR capacitor is too high, it could lead to excessive peaking in the frequency response, which would reduce phase margin and potentially destabilize the system.