Y.li
Member level 2
Hello,
I am making an op-amp ckt (LM 324 with 5v single supply). I am facing some problems in that. Pls. see if anyone can help.
The op-amp is connected in open loop which gets input at its non inverting terminal. When there is no input, there is an bias voltage of 0.3 v. To get zero output at this condition, the inverting terminal is biased with 0.5 v.
The ckt works ok in the unloaded condition. But when I connect a load to the o/p of this op-amp the ckt does not give the required output.
The load is an LED with 10K current limiting resistor and an i/p of a AND gate (with a10k grounding resitor) in parallel. When the non inverting pin is low, the output of the op amp should be low and the LED & AND gate o/p should be low. But that is not the case. Both the outputs remain high.
When I checked the voltage at the inverting and non inverting pin, both of them shift to 0.5 v (where as the voltage from the previous stage, connected to the non inverting terminal is zero). This is true if I change the bias voltage to any other voltage also; eg. 0.6 v.
I tried by inserting an op-amp buffer between the load and the output of op-amp. That didnt work.
Thanks,
Y. Li
I am making an op-amp ckt (LM 324 with 5v single supply). I am facing some problems in that. Pls. see if anyone can help.
The op-amp is connected in open loop which gets input at its non inverting terminal. When there is no input, there is an bias voltage of 0.3 v. To get zero output at this condition, the inverting terminal is biased with 0.5 v.
The ckt works ok in the unloaded condition. But when I connect a load to the o/p of this op-amp the ckt does not give the required output.
The load is an LED with 10K current limiting resistor and an i/p of a AND gate (with a10k grounding resitor) in parallel. When the non inverting pin is low, the output of the op amp should be low and the LED & AND gate o/p should be low. But that is not the case. Both the outputs remain high.
When I checked the voltage at the inverting and non inverting pin, both of them shift to 0.5 v (where as the voltage from the previous stage, connected to the non inverting terminal is zero). This is true if I change the bias voltage to any other voltage also; eg. 0.6 v.
I tried by inserting an op-amp buffer between the load and the output of op-amp. That didnt work.
Thanks,
Y. Li