op-amp based bandgap reference phase margin test

[anhnha]

I am measuring phase margin for this bandgap using iprobe from analogLib in Cadence by breaking the loop and inserting iprobe between the output of op amp and gate of two top transistors. However, the problem is that I have heard that this method doesn't work for circuit that has more than one loop.
If so, how can I measure phase margin in Cadence for this type of bandgap?
Any help is appreciated!

 

[yuvan]

No. As long as you break the loop in a way that doesn't have any other inherent minor loop inside it, the loop analysis will give you proper results. If you are breaking the loop at the opamp output, then you are injecting equal test signal to both the loop, so that should give you proper results.

 

[anhnha]

Thank you.

With that measurement, I got phase margin 15 degree. However, when I run transient analysis with step voltage at the input, the transient response doesn't show any ringing at all, and settling time is very long about 10ms.

**broken link removed**

 

[yuvan]

Can you post the schematic of stb analysis and the waveforms..

 

[anhnha]

Hi.
Here is the phase margin and schematic:
https://www.dropbox.com/s/rw2ns9nelmmqvpt/Phase Margin.png
https://www.dropbox.com/s/qbu35k66vjpv8uk/BG.JPG

As you can see PM = 17 degree but transient response shows no ringing.

 

[Dominik Przyborowski]

You should insert probe before inp input of opamp not at it output.

 

[LvW]

You should insert probe before inp input of opamp not at it output.

Yes - that´s correct.
In case of two loops of equal "degree" you must open the positive feedback loop only. Otherwise you loose the dc operating point (stabilized by negative feedback).
However, one can argue if this gives the "correct" phase margin because your circuit has three loops (negative, positive and combined). Thus, we can define three different loop gains and three different margins.
Of course, the "positive" loop alone causes instability and the whole circuit is stabilized applying additional negative feedback - and it is common practice to proceed as described (negative loop remains closed).

 

[anhnha]

Thank you!

Dominik Przyborowski:

You should insert probe before inp input of opamp not at it output.

Could you explain why? Sometimes, it is really confusing. I don't know where to put the probe. What determine the location of the probe?
LvW:
Could you answer the questions above?
What is the third loop?
I can't see it.
Could you suggest how to measure phase margin for this circuit?
I think you meant to say that we have to measure three times and finally add them together to get the total phase margin. Is that right?

I have just put the "iprobe" at the non-inverting of opamp and phase margin is 27 degrees. However, why transient response still shows no ringing at all?

 

[LvW]

anhnha, I think it is answered already:

* In order to avoid loading errors you must open the loop at a node where a high impedance is connected to a "source" impedance which is much smaller (positive feedback loop at the opamp output or at the input)
Examples:
Output resistance of some ohms conncted to resistors in the kOhm range, or
Feedback resistors connected to the large opamp input resistor.

* Three loops: (a) positive closed (negative open), (b) negative closed (positive open), (c) both open.
As I have mentioned: Apply method (b).

* I cannot comment on the "i-probe" method. Why don´t you try the classical method with ac voltage injection (method(b)).

 

[anhnha]

Thank you, LvW.

I will try the classical method. But before that could you confirm this?
I will insert an inductor 1G H between drain of P1 and the point A in the picture post #1.
Next connect an ac signal in series with a large cap 1M F at the non-inverting of opamp.
Is that correct?

 

[FvM]

As already discussed, your circuit has multiple feedback loops.

I think, the loop that's mainly interesting for stability analysis and compensation is the loop through the OP output which splits into the P1 and P2 loop. In so far, I won't analyze the loop through P1 only.

You can easily cut the feedback loop for signal pathes with Zsource << Zload or Zsource >> Zload. P1 drain node doesn't meet either condition, you have to apply the "extended" Middlebrook method to keep the original loop gain. If P1 Ro can be assumed >> R1, the intended inductor circuit woould neither work because it's only suited for Zsource << Zload.

 

[yuvan]

Hi FvM,

I assume when we break the loop at the output of the opamp, then too we are defining the DC bias points by both the loops (Let say breaking the loop the traditional way). And also for eg, lets take const gm circuit with resistor degeneration on NMOS side. Then LG by breaking NMOS Gate ans Breaking the loop at the PMOS gate give two different results (As already mentioned by you). But breaking the loop at the PMOS gate makes sense because you get a loop gain of more that unity --> which makes sense, becos current always stabilizes to the proper value, in case of any disturbance and doesn't stay there...which it should if it had a loop gain of unity.. So, breaking at the gate of the PMOS means you are injecting equal signal to both the +ve & -ve loops, which makes sense too, since we are ultimately intereted in the overall effective loop gain. This is what I understood (for a long time now). But willing to change if you can point out where I'm wrong. Having said this I don't have any clue why anhnha is getting 15 deg and still no ringing.

But anhnha having a probe at the input of the amp gives you proper results?

 

[LvW]

anhnha, I agree with everything FvM wrote.
However, I think you could try to apply the inductor method for the opening between point A and the opamp input. This should avoid unacceptable loading errors.
As an alternative, of course you could try to open BOTH loops (directly at the opamp output using an inductor). However, due to my experineces sometimes this gives uncorrect simulation results - at least if the open-loop gain of the opamp is very large.

EDIT: It is an old and heavily discussed problem: In a multi-loop system, is there a dominant loop which is responsible for the real phase margin? And what does this mean: Real margin?
The situation is clear: If you can define n different loops you have n different ways to open the loop(s) with n different margins.
This is not surprising at all because this is in accordance with the DEFINITION of a phase margin: Additional phase shift within the particular loop which brings the circuit to the stability limit.

But the main question is (also in this case): Which loop resp. which margin mostly determines the transient behaviour?
For my opinion there is no general answer - unless you can define an outer loop (in addition to other local loops, which mostly have a much smaller time constant).

 

[anhnha]

Thank you, everyone.

Sorry but I can't understand what you said, so please help me explain it.
What is Zsource and Zload you are referring to?

 

[FvM]

Zsource and Zload = left and right side where you cut the loop. E.g. for P1 drain node, Zsource is MOSFET output impedance, Zloadf is R1 + Zin Q1.

 

[dgnani]

I am measuring phase margin for this bandgap using iprobe from analogLib in Cadence by breaking the loop and inserting iprobe between the output of op amp and gate of two top transistors. However, the problem is that I have heard that this method doesn't work for circuit that has more than one loop.
If so, how can I measure phase margin in Cadence for this type of bandgap?
Any help is appreciated!

Hi anhnha,

I will not subscribe to all the advice you have received here so far; I have had my fair share of pain with similar bandgap stability issues so I had to do a fair share of digging:
- 'cutting' all loops with iprobe (or simply a 0V source) is exactly what Tian method requires (which is what spectre stb analysis uses); there are ways to deal with other fully differential designs but here you are lucky enough you can spare yourself the pain as here there is one net you can use to place iprobe (you found it: bravo!); stb will return the differential loop gain of this circuit
- by the way a 0V source does not open the loop so the OP and loading effects are still undisturbed; there is actually more happening under the hood since the location of the probe is used for both current and voltage injection (see Tian paper)
- what is perplexing is that you do not get ringing at 15deg of phase margin but here is the real question: what do you think is the input?! there is no input here besides perhaps the temperature (good luck putting a step on that) so how did you place your voltage step?
- bad idea using dropbox links and then deleting the files...

Hope this helps, I'd be curious to hear about it if you found a solution (thanks)