spear verilog
As the other people have said, a background in OOP is helpful, but not absolutely necessary to start Systemverilog.
Systemverilog has several different areas of focus: design & modeling (RTL), verification (TB), assertions & coverage.
The verification(TB) aspect is definitely the most challenging. And here's where a background in OOP, or another HVL (like e or VERA) really helps.
I would focus on learning the RTL constructs first, practice them a little bit, then tackle the TB constructs next.