# one output, two drivers; Xilinx gives Error but the design works in iVerilog

Status
Not open for further replies.

#### ebichuhamster

##### Newbie level 4
the module
Code:
module d_l2(rst,en,clk,in,o);
input rst,en,clk,in;
output reg o;            //=1'b10000000;
always @ (clk or en or in)
if(~clk)
begin
o=en&in;
//$display("en=%b-in=%b",en,in); end else begin o=en&1'b1; end always @ (rst) begin o=0; end endmodule The error is ERROR:HDLCompiler:1401 - "C:\Users\ProyectoFinal\d_l2.v" Line 34: Signal o in unit d_l2 is connected to following multiple drivers: Driver 0: output signal of instance Ground (GND_5_o_BUF_2). Driver 1: output signal o of instance Multiplexer (en_en_MUX_137). Module d_l2 remains a blackbox, due to errors in its contents I understand that I have much to learn, but the deadline is monday and this thing works. I just need Xilinx to draw the circuits and then I probably wont use it again for some time. It makes sense to me that there would be a conflict, but these two statements occur on a different state of the clock, and it does indeed work properly when i run the testbench on iverilog. If anyone has any ideas as to how to tell Xilinx to ignore this error (it wont synthethize because of this) or better yet to solve it Thank you. #### rca ##### Advanced Member level 4 You need to learn how to write a flop. #### ebichuhamster ##### Newbie level 4 #### dave_59 ##### Advanced Member level 3 A forum is not the place to learn Verilog. Look for a tutorial. #### ebichuhamster ##### Newbie level 4 A forum is not the place to learn Verilog. Look for a tutorial. I have to apologize then. I'll go lose another week to learning all that I can. Clearly i lost the first one. Since I don't know anything about verilog. #### ads_ee ##### Full Member level 6 I have to apologize then. I'll go lose another week to learning all that I can. Clearly i lost the first one. Since I don't know anything about verilog. Are you saying it took a week to write that "flip flop"? A quick search on Google with "verilog flip flop example code" results in the 2nd find: https://eesun.free.fr/DOC/VERILOG/synvlg.html#d type ff with async reset In that you'll see that a flip flop is coded in a single always block. Clearly learning how to code synthesizable (Xilinx XST) Verilog isn't that difficult to do with a little research. Regards, -alan ebichuhamster ### ebichuhamster Points: 2 Helpful Answer Positive Rating #### ebichuhamster ##### Newbie level 4 First of all, I appologize if I was untowards. Are you saying it took a week to write that "flip flop"? Not at all. There are many other modules. But as I stated, I only have 1 week of exposition to verilog. For this reason it's been rather difficult (coming from an eclipse/java environment) to debug and generally understand what is going on. I finally discovered that the$display (function?) can be used outside the testbench (i do not know why i imagined otherwise). With this i got the testbench to run properly. After this I found out xilinx can be used to 'synthethize' (something im still vague on) and just draw the circuit schematics. After so many hours of not knowing what I'm doing, and downloading the whole of xilinx (not so fast connection) i find that it won't synthethize. It stated the error and it made sense, but the testbench ran properly on iverilog. I thought i could come here and get a quick answer and allow myself not to redesign my working code because of xilinx being overly strict (or possibly too right for my purposes).

Indeed i have found many flip flop examples online. And I tried them when I had no idea what I was doing. Then I redesigned the modules and combined what is supposed to be a switch array module that outputs unto a dflop array. The code that I posted (i think) is supposed to work with this switch array in mind, hence an enable signal is one of its inputs. After combining the modules was that I discovered the \$display (task?) and rather promptly had it working.

I can go into detail about what I wanted to do, what I did, or the rest of my code. And it may serve me in the future, but I won't be working on that code again anytime soon. I had to draw the schematic by hand (visio) as I was running out of time and i found that to be my quickest option. I was criticized for not modelling a raw flip flop, as was expected, but then again it worked.

I expect to not come here again. I might regret it in the future, as I have indeed liked how verilog works (after it made sense at least). But frankly I don't wish to be a part of a forum that will shun so severely someone who clearly doesn't dominate the material.

#### dave_59

##### Advanced Member level 3
ebichuhamster,

I don't think anyone was trying to shun you, just offering advice on better places to look for help. I don't think a discussion forum is the place to learn a new language like Verilog from scratch and in a rush. There is already a lot of material typed up in the form of tutorials and examples that can be easily searched much faster than anyone can type here.

Status
Not open for further replies.