One cycle delay vhdl

[needhelp123]

In need of help, I have a program here which I need to submit next week. I just need to add in 1 cycle clock delay but I have no idea how.
This is my code

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Code VHDL - [expand]
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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
ENTITY fpga is
port(
    data_clk: in std_logic;
    data_out: out std_logic;
    data_in: in std_logic;
    osc: in std_logic;
    rst: in std_logic;
    LED: out std_logic
    );
END fpga;
 
ARCHITECTURE behaviour of fpga is 
signal counter: integer range 0 to 7;
signal data: std_logic;
signal output2: std_logic_vector(7 downto 0);
signal receiving: std_logic_vector(7 downto 0); 
begin
    
    process(osc,rst)    
        begin 
                if(rst = '0') then          -- reset button pressed
                counter <= 0;               -- counter will show 0
                output2 <= "01000110";      -- output2 still running
                LED <= '1';                 -- LED will not light up
                data_out <= '0';
                
            elsif (rising_edge(osc)) then   
                receiving <= receiving(6 downto 0) & data_in;   --shifts the bottom seven bits of receiving left by one
                                                                --puts the new data bit from the data_in to bit 0 of dat_reg
            
            
                if (data_in = data_out) then                    -- compare data_in & data_out
                    LED <= '0';
                else
                    LED <= '1';
                end if;
 
                    if(counter < 7) then
                        counter <= counter + 1;
                    else
                        counter <= 0;
                    end if;
                    
                    case counter is             -- Transmitter
                        when 0 =>
                            data_out <= output2(0);
                        when 1 =>
                            data_out <= output2(1);
                        when 2 =>
                            data_out <= output2(2);
                        when 3 =>
                            data_out <= output2(3);
                        when 4 => 
                            data_out <= output2(4);
                        when 5 => 
                            data_out <= output2(5);
                        when 6 =>
                            data_out <= output2(6);
                        when 7 =>
                            data_out <= output2(7);
                        when others => 
                            data_out <= '0';    
                    
                    end case;                   
            end if;
    end process;
end behaviour;

---

 

[vipinlal]

suppose you want to delay a signal named temp, then you can do it like this:

if(rising_edge(clk)) then
   temp_delay <= temp;
end if;

 

[needhelp123]

They state that it is a Misspelled variable, signal or procedure name?. Do I have to declare any signal?

 

[TrickyDicky]

yes. Think about what circuit you are describing - each register needs a separate name.

 

[AdvaRes]

I modified your code but didnt test it coz I dont have a simulator.
Please tell me what you get with this code.

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Code VHDL - [expand]
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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
ENTITY fpga is
port(
data_clk: in std_logic;
data_out: out std_logic;
data_in: in std_logic;
osc: in std_logic;
rst: in std_logic;
LED: out std_logic
);
END fpga;
 
ARCHITECTURE behaviour of fpga is
signal counter: integer range 0 to 7;
signal data: std_logic;
signal output2: std_logic_vector(7 downto 0);
signal receiving: std_logic_vector(7 downto 0);
begin
 
process(osc,rst)
variable tmp: std_logic;                            -- <----------------------------Variable used in the process
begin
 
 
tmp:=data                                           -- <----------------------------Output result 
data_out<=tmp
if(rst = '0') then -- reset button pressed
counter <= 0; -- counter will show 0
output2 <= "01000110"; -- output2 still running
LED <= '1'; -- LED will not light up
data_out <= '0';
 
elsif (rising_edge(osc)) then
receiving <= receiving(6 downto 0) & data_in; --shifts the bottom seven bits of receiving left by one
--puts the new data bit from the data_in to bit 0 of dat_reg
 
 
if (data_in = data_out) then -- compare data_in & data_out
LED <= '0';
else
LED <= '1';
end if;
 
if(counter < 7) then
counter <= counter + 1;
else
counter <= 0;
end if;
 
case counter is                                              --     <---------------------------Memorise the result
when 0 =>
data <= output2(0);
when 1 =>
data <= output2(1);
when 2 =>
data <= output2(2);
when 3 =>
data <= output2(3);
when 4 =>
data <= output2(4);
when 5 =>
data <= output2(5);
when 6 =>
data <= output2(6);
when 7 =>
data <= output2(7);
when others =>
data_out <= '0';
 
 
end case;
end if;
end process;
end behaviour;

---

 

[TrickyDicky]

Apart from the syntax errors, that makes no difference to the code, as you put the variable assignment before the output signal assignment. Hence it just makes a wire. Plus its not even in the clock branch.
Terrible example AdvaRes

 

[sagar.bavane]

on which signal u want one cycle dealy...?

 

[AdvaRes]

@TrickyDicky,
The output signal assimement can be as indicated in the code or like you mentioned in the clock branch. Another mistake in declaring the variable, it should be before the begin. I corrected it.
I have no simulator to verify it. I gave just the idea.

 

[TrickyDicky]

It will not work the way you wrote it. It will NOT add an extra pipeline delay. It is very poorly written code.

 

[AdvaRes]

@TrickyDicky
With all my respect Sir, we dont need a troll to comment our posts in this forum.
If you are cleaver answer the question.


@needhelp123
Please try this one and let me know.

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Code VHDL - [expand]
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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
ENTITY fpga is
port(
data_clk: in std_logic;
data_out: out std_logic;
data_in: in std_logic;
osc: in std_logic;
rst: in std_logic;
LED: out std_logic
);
END fpga;
 
ARCHITECTURE behaviour of fpga is
signal counter: integer range 0 to 7;
signal data: std_logic;
signal output2: std_logic_vector(7 downto 0);
signal receiving: std_logic_vector(7 downto 0);
begin
 
process(osc,rst)
begin
if(rst = '0') then -- reset button pressed
counter <= 0; -- counter will show 0
output2 <= "01000110"; -- output2 still running
LED <= '1'; -- LED will not light up
data_out <= '0';
 
elsif (rising_edge(osc)) then
receiving <= receiving(6 downto 0) & data_in; --shifts the bottom seven bits of receiving left by one
--puts the new data bit from the data_in to bit 0 of dat_reg
 
 
if (data_in = data_out) then -- compare data_in & data_out
LED <= '0';
else
LED <= '1';
end if;
 
if(counter < 7) then
counter <= counter + 1;
else
counter <= 0;
end if;
 
case counter is -- Transmitter
when 0 =>
data <= output2(0);
when 1 =>
data <= output2(1);
when 2 =>
data <= output2(2);
when 3 =>
data <= output2(3);
when 4 =>
datat <= output2(4);
when 5 =>
data <= output2(5);
when 6 =>
data <= output2(6);
when 7 =>
data <= output2(7);
when others =>
data <= '0';
 
end case;
 
data_out<=data
 
end if;
end process;
end behaviour;

---

 

[needhelp123]

I still couldn't get the one clock cycle delay. It makes no difference from the code I've given, the LED will still light up even though I didn't connect the wires. It should only light up when I short the pins

- - - Updated - - -

on which signal u want one cycle dealy...?

I need 1 cycle delay on the dataout

 

[sagar.bavane]

@needhelp123
plz check i hav added delay in data_out.... by making some miner chenges....

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
ENTITY fpga is
port(
data_clk: in std_logic;
data_out: inout std_logic;
data_in: in std_logic;
osc: in std_logic;
rst: in std_logic;
LED: out std_logic
);
END fpga;
 
ARCHITECTURE behaviour of fpga is
signal counter: integer range 0 to 7;
signal data: std_logic;
signal output2: std_logic_vector(7 downto 0);
signal receiving: std_logic_vector(7 downto 0);
signal add_delay: std_logic; 
begin
 
process(osc,rst)
begin
if(rst = '0') then -- reset button pressed
counter <= 0; -- counter will show 0
output2 <= "01000110"; -- output2 still running
LED <= '1'; -- LED will not light up
 
receiving<= X"00";
data<='0';
 add_delay<='0';
elsif (rising_edge(osc)) then
receiving <= receiving(6 downto 0) & data_in; --shifts the bottom seven bits of receiving left by one
--puts the new data bit from the data_in to bit 0 of dat_reg
 
 
if (data_in = data_out) then -- compare data_in & data_out
LED <= '0';
else
LED <= '1';
end if;
 
if(counter < 7) then
counter <= counter + 1;
else
counter <= 0;
end if;
 
case counter is -- Transmitter
when 0 =>
data <= output2(0);
when 1 =>
data <= output2(1);
when 2 =>
data <= output2(2);
when 3 =>
data <= output2(3);
when 4 =>
data <= output2(4);
when 5 =>
data <= output2(5);
when 6 =>
data <= output2(6);
when 7 =>
data <= output2(7);
when others =>
data <= '0';
 
end case;
 add_delay<= data;
end if;
 
end process;
--data_out<=add_dealy;
 
process(osc,rst)
  begin
     if rst='0' then
        data_out<='0';
       
     elsif (rising_edge(osc)) then
        --add_delay<= data;
        data_out<= add_delay;
    end if;
  end process;
 
end behaviour;

---

 

[needhelp123]

The LED still doesn't turn off when I did not short the 2 ports. It should be offed, and the LED will only light up when the 2 ports are short together

 

[sagar.bavane]

check this simulation

 

[needhelp123]

Then how can I make receiving the same as output2 ?

 

[sagar.bavane]

give that output2 to respective receving signal thats all......
receiving<= output2;

 

[needhelp123]

Is it possible to not make data_in always '1' ?

 

[sagar.bavane]

sure...y not...
but in ur code its input so we dnt hav controll on it...
if u wnt to use it as always '1' then make it internal signal ans during initialisation itself assign it to '1' and remove that data_in input from entity.....thats all...

 

[needhelp123]

However in the simulation you gave, 'data_in' is always '1'. Is there another way to make receiving = output2 without internal altering of the code as I have to do it externally via output and input pins?

 

[sagar.bavane]

in simulation i hav taken it '1' it dosent mean it should be always '1'.... its not in our control u can take it '0' and test it see the results.....wether its according to ur requirments of funtionality.....