On DNL/INL with reduced bits

[abonic]

Hi, guys
If I only use the MSB K bits of a nominal N bits ADC (N>K), what's the relationship between the MSB K bits DNL/INL and N bits DNL/INL.

To give the question more apprehensible, assume the max DNLs/INLs for the MSB K bit and the nominal N bits are\[ DNL_K\]/\[INL_K\], and \[DNL_N\]/\[INL_N\] separately.

Can we have the following conclusions
\[DNL_N=2^{N-K}DNL_K\]
\[INL_N=2^{N-K}INL_K\]

Or there exists other statistical relationships

Thank You!

 

[erikl]

No, I don't think this will work, sorry: a reasonably good ADC shouldn't have DNL-, even INL-values greater than a few single bits (at least for N≦12), generally I'd estimate less than 2^N-7.. 2^N-8 bits, see e.g. here for a 10bit converter:
.
That means if you measure the DNL/INL values on the MSB K=8 for this N=10 bit converter, you'd get zero values as results.

 

[abonic]

Yeah, I understand what you mean in your case.
Let's now think about a bad case, where an 10-bit ADC has 16-LSB maximum DNL and 32-LSB maximun INL. What if we only use the MSB 9-bit to calculate DNL & INL, can we obtain 8-LSB maximun DNL and 16-LSB maximum INL for MSB-9 bit data.

 

[erikl]

... a bad case, where an 10-bit ADC has 16-LSB maximum DNL and 32-LSB maximun INL.

The other way round, usually: INL > DNL.
Anyway, such a bad ADC I'd through far, far away! ;-)

What if we only use the MSB 9-bit to calculate DNL & INL, can we obtain 8-LSB maximun DNL and 16-LSB maximum INL for MSB-9 bit data.

Sure, in such case - with N-K=1 (max. =2) - your above equations would work correctly.

 

[abonic]

It only a theoretical discussion, not a real case.