On-chip debugging - any info?

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vsop

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On-chip debugging

Hi,

Dose anybody hear anything about "on-chip debugging"? It looks like

the ICE from the user's point of view, but some circuits have to built in

the chip by the chip vendor.

Any information is welcome.
 

Re: On-chip debugging

vsop said:
Hi,

Dose anybody hear anything about "on-chip debugging"? It looks like

the ICE from the user's point of view, but some circuits have to built in

the chip by the chip vendor.

Any information is welcome.
Click to expand...

Hi welcome from the stone age.
The most popular and low cost is the JTAG interface
(some chips also have own serial interface debug like PIC).

The first use of the jtag is for boundary scan for test the io pin of the chip
and the system ,and also if you have a clear flash you can prog it by the
pin change of the chip.

Other chips (is most popular in dsp) you can use the interface also for
debbug the chip.

They have not the full power like a real ice for real time(the jtag connected to lpt or serial of the pc),
but they have a lot of funtionaly for debbuging(break poits read register some capture,prog mem, dump mem,etc..).


Best regards. 8)
 

OCD

hi vsop... i have found a paper

it begins with bdm but this is one variant of ocd... and it explain the other variants for a on chip debugging

i hope it will help you ;-)

look at h**p://w*w*w.macraigor.com/zenofbdm.pdf
 

Thanx for your information.
I'm working on a new project which contains several IPs including MCU. Due to the pin count limitation, it's very hard for us to build any ICE companion FPGA beside this SOC. Therefore, I'm looking for any information about how to build up the internal on-chip debug circuits. What I prefer is something like that from FS2(**broken link removed**), but I can build that by myself.
I'm still awaiting any advice, thanx.
 

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