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On-chip communication protocol like AMBA AHB

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mido11

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Hi all,

I have some difficulty by understanding the reason why only one master can own the bus system at the time even if another master do not want to access the same target which responds the first master request.

which penalty shall the bus to face if it is suitable to deal with this option?

Thanks
Mido
 

ckshivaram

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CoreAHB contains a fixed, priority-based, arbitration scheme that supports three AHB bus masters as well as the dummy master. The priority allocation is as follows:
• Master 3 has the highest priority
• Master 0 (dummy master) has the second highest priority
• Master 2 has the middle priority
• Master 1 has the lowest priority and is the default bus master. The main subsystem processor (such as CoreMP7) is normally connected to this master connection.
 

mido11

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Thnaks for your answer, but my question still not answered.

If I want to increase the throughput of the system then I can let more than one master access the bus at the same time if they not request the same target.

Why this simple but efficient option is not implemented by most on-chip communication buses.

Could the reason be that the size of the bus became huge when considering this option? But I am not really agree with that...

Any help..
 

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